We report on the CMOS-compatible hybrid III-V/Silicon platform developed in CEA-LETI. In order to follow the large-scale integration capabilities of silicon photonics, already available worldwide in 200mm or 300mm through different foundries, the development of CMOS-compatible process for the III-V integration is of major interest. The technological developments involve not only the hybridization on top of a mature silicon photonic front-end wafer through direct molecular bonding but the patterning of the III-V epitaxy layer, low access resistance contacts, as well as planar multilevel BEOL must also be investigated and optimized. Test vehicles for the process validation based on either distributed feedback (DFB) or distributed Bragg reflector (DBR) laser cavities were designed. A modular approach is proposed in order to minimize the impact on the already qualified silicon photonics devices. Next, a collective III–V die bonding and processing have been successfully developed in this platform. The collective bonding, based on a flexible template holder, allows for large scale die to wafer transfer in both 200 and 300mm. After the III-V substrate removal and III-V patterning relying on optimized dry etching processes, CMOS compatible metallization’s are used to realize ohmic contact on n-InP and P-InGaAs leading to contact resistivity in the range of 10−6 Ω·cm². While first demonstrations have been obtained through wafer bonding, the fabrication process was subsequently validated on III-V dies bonding with a fabrication yield of Fabry-Perot lasers of 97% in 200mm. A planarized two-metal-level BEOL was used to connect the devices, leading to a drastic reduction of series resistance between 5.5 and 7 Ω. Finally, the functionality of DFB and DBR lasers is demonstrated with SMSR up to 50 dB and maximum output power of 3 mW in CW. The overall technological features are expected improve the efficiency, density, and cost of silicon photonics PICs.
Silicon nanophotonics represents a scalable route to deploy complex optical integrated circuits for multifold applications, markets, and end-users. Most recently, applications such as optical communications and interconnects, sensing, as well as quantum-based technologies, among others, present additional opportunities for integrated silicon nanophotonics to expand its frontiers from laboratories to industrial product development. Within a wide set of functionalities that silicon nanophotonic chips can afford, the availability of low-loss optical input/output interfaces has been regarded as a major practical obstacle that hampers long-term success of integrated photonic platforms. Indeed, fiber-chip interfaces based on diffraction gratings are an attractive solution to resonantly couple the light between planar waveguide circuits and standard single-mode optical fibers. Surface grating couplers provide much more alignment tolerance in fiber attach compared with most conventional edge-coupled alternatives, while retaining the much-needed control of the fiber placement on the chip surface and wafer-level-test capability that the in-plane convertors lack. Here, we report on our recent advances in the development of high-performance fiber-chip grating couplers that exploit the blazing effect. This is achieved with well-established dual-etch processing in interleaved teeth-trench arrangements or using L-shaped grating-teeth-profile geometries. The first demonstration of the L-shaped-based grating coupler yielded a coupling loss of -2.7 dB, seamlessly fabricated into a 300-mm foundry manufacturing process using 193-nm deep-ultraviolet stepper lithography. Moreover, silicon metamaterial L-shaped fiber couplers may promote robust sub-decibel coupling of light, reaching a simulated coupling loss of -0.25 dB, while featuring device layouts (>120 nm) compatible with lithographic technologies in silicon semiconductor foundries.
The 3D-AFM technique is a very well known technique as a non destructive reference to calibrate CD-SEM and
Scatterometry metrology. However, recent hardware, tip design and tip treatment improvements have offered to the
technique new capabilities that pave the way for multiple applications in the semiconductor industry. The 3D-AFM
technique is today not only a calibrating technique but also a process control technique that can be use either at the R&D
level or in fab environment.
In this paper, we will address the limits of the 3D-AFM technique for the semiconductor industry depending on the
applications by focusing our study on tip to sample interactions. We will identify, test and validate potential industrial
solutions that could extend the 3D-AFM potentialities. Subsequently, we will show some interesting applications of the
technique related to LER/LWR transfer during silicon gate patterning and related to advance multiwires devices