6% attenuated embedded PSM (att-EAPSM) has been widely used in semiconductor wafer
manufacturing industry at 130nm, 90nm, 65nm and 45nm nodes. To effectively use the 6% att-EAPSM
photomask technology and reduce its manufacturing costs, it is important for the industry to develop a
comprehensive mask specification that can fully meet the wafer level lithography requirements without
over-constraining the control parameters in 6% att-EAPSM manufacturing process. In this paper, we used
computer simulation software, Prolith by KLA-Tencor to study the impact of local phase-angle and
transmission errors to wafer lithography process. The simulation results indicated that phase-angle and
transmission errors result in a best focus plane shift, and hence reduce the common focus exposure window
across the mask. The data also indicated that as the NA (numerical aperture) of the lithography system
increases, the same amount of phase-angle error results less amount of focus shift. Based on this study and
the practical common focus windows in semiconductor industry, we proposed a new phase-angle and
transmission specification of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer process.
The lithography prognosticator of the early 1980's declared the end of optics for sub-0.5&mgr;m imaging. However, significant improvements in optics, photoresist and mask technology continued through the mercury lamp lines (436, 405 & 365nm) and into laser bands of 248nm and to 193nm. As each wavelength matured, innovative optical solutions and further improvements in photoresist technology have demonstrated that extending imaging resolution is possible thus further reducing k1. Several author have recently discussed manufacturing imaging solutions for sub-0.3k1 and the integration challenges.
Our industry will continue to focus on the most cost effective solution. What continues to motivate lithographers to discover new and innovative lithography solutions? The answer is cost. Recent publications have demonstrated sub 0.30 k1 imaging. The development of new tooling, masks and even photoresist platforms impacts cost. The switch from KrF to ArF imaging materials has a significant impact on process integration. This paper will focus on the usefulness of beyond water immersion for 22nm logic node. Data will be presented demonstrating the impact of higher refractive index photoresist systems have on the further extension of ArF Immersion.
As semiconductor gate lengths shrink, photoresist trends toward thinner films. Thick photoresist films are not desirable because they tend to absorb more light, require higher energies to pattern, increase pattern collapse, and subtract from depth of focus and exposure latitude. The minimum thickness of implant photoresist is governed by the stopping power of the photoresist for the ion type and the energy of the implant. Relatively high energy implants and/or lower ion stopping power in the photoresist require thicker photoresist films. These problems can be mitigated through a novel photoresist fluorination process. The fluorination process results in the replacement of H atoms by heavier F atoms effectively increasing the molecular weight of the fluorinated film and its ability to block ion implantation. This straightforward and cost-effective process is investigated for use with a standard 248 nm dyed photoresist. Substrate damage probe measurements and Secondary Ion Mass Spectrometry depth profiles show species-dependent ion implant masking improvements of up to 40 % for fluorinated photoresist versus as-developed photoresist. Geometric and process margin arguments are discussed for thinning photoresist where angled implants are needed or process capability is insufficient. Finally, electrical data is presented that demonstrates the manufacturability of these fluorinated and thinned photoresist films.
One of the consequences of low-k1 lithography is the discrepancy between the intended and the printed pattern, particularly in 2-D structures. Two recent technical developments offer new tools to improve manufacturing predictability, yield and control. The first enabling development provides the ability to identify the exact locations of lithography manufacturing "hot spots" using rigorous full-chip simulation. The second enabling development provides the ability to efficiently measure and characterize these critical locations on the wafer. In this study, hot spots were identified on four critical patterned layers of a 90nm-node production process using the Brion Tachyon 1100 system by comparing the design intent GDS-II database to simulated resist contours. After review and selection, the detected critical locations were sent to the Applied Materials OPC Check system. The OPC Check system created the recipes necessary to automatically drive a VeritySEM CD SEM tool to the hot spot locations on the wafer for measurements and analysis. Using the model-predicted hot spots combined with accurate wafer metrology of critical features enabled an efficient determination of the actual process window, including process-limiting features and manufacturing lithography conditions, for qualification and control of each layer.
Patterning of sub-100nm contacts for sub-90-nm-node devices is one of the primary challenges of photolithography today. The challenge involves achieving the desired resolution while maintaining manufacturable process windows. Increases in numerical aperture and reductions in target CDs will continue to shrink process windows and increase mask error factor resulting in larger CD variation. Several techniques such as RELACS, SAFIER, and resist reflow have been developed to improve the resolution of darkfield patterns such as contacts and trenches. These techniques are all post-develop processes applied to the patterned resist. Reflow is a fast process with low cost of ownership, but has two major disadvantages of high temperature sensitivity and large proximity bias. SAFIER and RELACS both have much slower throughput and higher cost of ownership than reflow. SAFIER also is sensitive to temperature and has large proximity bias. In this paper, a novel process is described that reduces the diameter of contact holes in resist up to 25nm without proximity effects. This process uniformly swells the resist film resulting in a shrink of patterned holes or trenches. Results are shown for 248nm and 193nm single layer resists, and a 193nm bilayer resist. This process has the potential to be high throughput with low cost of ownership similar to reflow techniques but without the proximity effects and thermal sensitivity observed with reflow.
A great deal of resources has been invested by the semiconductor industry as a whole to make ready 157 nm as the next lithography technology node. Despite of all this effort serious infrastructure issues remain to be solved. Perhaps the first one is the availability of CaF2, but a close second is a suitable soft-pellicle material. It has been previously reported that standard 193nm materials, like Teflon AF and Cytop, fail catastrophically upon exposure at 157nm radiation; and that their transmission is very poor to non-existent. In this paper we report data showing that these materials have higher transmission and lifetimes than previously thought. The physical lifetime of Cytop of nearly 500 J/cm2 is remarkably high, although the transmission varies as a function dose suggesting physical and chemical changes from the onset. For Teflon AF the transmission is a more complex function of exposure dose, suggesting competing mechanisms. From experiments run with PVDF (polyvinyl difluoride), we conclude that the widely reported photodarkening effect is due to the presence of hydrogen in close proximity to a fluorine atom. From IR spectra we conclude that the dioxole moeity in Teflon AF undergoes a series of photochemical reactions that lead to the physical destruction of the polymer.
Typically resist performance has lagged behind exposure tools as new, shorter wavelengths are introduced in the never-ending industry quest to print smaller features. Over time, however, the performance improves until it matches or exceeds that of the resists used in the previous wavelength node; 193 nm resists have not been the exception. Their resolution and stability has improved but one issue that remains is linewidth slimming. This phenomenon consists in a reduction of resist features when they are exposed to an electron beam in an scanning electron microscope during linewidth metrology. Although this phenomenon has been well described and reasonably well understood, no solution exists to eliminate this problem. In this paper we show linewidth slimming can be significantly reduced by fluorinating the resist after the relief image has been developed, keeping the lithographic dimensions unchanged.
Resist pattern edge roughness is expected to cause degradation of transistor performance as gate lengths shrink below 40 nm. In the literature line edge roughness (LER) has been linked to many optical and chemical variables associated with the lithography process. As resist trim etch becomes more aggressive over time, LER on etched gates becomes less linked to the roughness in resist, and more to a product of the coupled lithography and etch processes. The aspect ratio of trimmed resist features increases and patterns become susceptible to pattern collapse, bending and tearing. Conversely if aspect ratios are maintained through the trim process, then the ability of the resist to protect the substrate from the final etch is degraded as the resist thickness decreases. A novel method of resist fluorination is presented that significantly reduces LER and pattern deformations such as collapse, tearing and bending. Experimental data shows that resist fluorination can make possible sub-30 nm etched polysilicon gates at aspect ratios on the order of 5:1. The same fluorination process yields LER improvements of 15% to 20% on average with largest improvements in the mid-range roughness frequencies of 10 - 50 μm-1. The length scale, or inverse of frequency, is also used in the study. The resist fluorination process is described as it is used in the study. Experimental and analytical data show how the process is reduced to practice and how LER and pattern deformation are improved. The fluorination process is simple to integrate into a standard wafer flow, has low cost of ownership, and yields large process improvements.
Due to the challenging CD control and resolution requirements of future device generations, a large number of complex lithography enhancement techniques are likely to be used for random logic devices. This increased design, reticle, process and OPC complexity must be handled flawlessly by process engineers in order to create working circuits. Additionally, the rapidly increasing cost and cycletime of advanced reticles has increased the urgency of obtaining reticles devoid of process limiting design or OPC errors. We have extended the capability of leading edge model-based OPC software to find and analyze process-limiting regions in real product designs. Specifically, we have implemented and verified software usefulness to find design-process limitations due to measured lens aberrations, as well as errors in focus, exposure or reticle CD control. We present results showing the applications and limitations of these new model-based analysis methods to discover process-design interaction errors in 90nm and 130nm patterning processes; and to propose design rule, process or OPC improvements to mitigate these errors.
The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (packing density) a scanner is also expected to provide tight control of the Across Chip Linewidth Variation, ACLV, (transistor speed). An important component of ACLV is lens aberrations. Techniques that measure in-situ the lens aberrations are now available. In a previous paper we reported good agreement between the first 25 Zernike coefficients measured in-situ using one of these techniques ARTEMIS and PMI (Phase Metrology Interferometry) data collected at the lens manufacturer. However questions have arisen as to the practicality of ARTEMIS, especially in view of its heavy reliance on a very large number of SEM images. We have measured the first 25 Zernike coefficients for 13 ASML 500/700 DUV Step & Scan systems in a high-volume wafer fab. In this paper we report on certain enhancements that were made to the best practice of ARTEMIS. We will also present a summary of the measurements taken and our first attempt to cluster the tools according to the aberrations measured.
Despite very intense work since its re-discovery in the early 1990’s, phase-shift lithography is only in limited use today. The reason for its lack of wide spread use is not performance, for the benefits of phase-shift lithography are very well documented in the literature. The problem has been the greater complexity involved in making phase shirt masks, the inspection and repair of defects, and in dealing with phase-shift conflicts and other layout problems. The phase shift approach most commonly used is attenuated phase-shift. This is not very surprising in view of the fact that this phase-shift approach requires only one write-pass; and the inspection, repair and OPC are less difficult than the other phase-shift options. Despite these shortcomings, work on phase shift continues as we push resolution and extend the life of optical microlithography. The reason is that the alternatives, 157 nm and next-generation lithography, have its own set of issues. As we come to grips with the complexities of working in the vacuum region of the spectrum, we realize that 157 nm is likely to be delayed, and more expensive than originally thought. All next generation lithography options require a great deal of new infrastructure, with it associated coast. In this paper we report on a self-aligned rim phase shift approach. There have been reports of self-aligned rim phase shift approaches before, however our approach is unique in that it only requires one write-pass. This significantly simplifies the mask-making process.
Aberrations, aberrations, here there everywhere but how do we collect useful data that can be incorporated into our simulators? Over the past year there have no less than 18 papers published in the literature discussing how to measure aberrations to answering the question if Zernikes are really enough. The ability to accurately measure a Zernike coefficient in a timely cost effective manner can be priceless to device manufacturers. Exposure tool and lens manufacturers are reluctant to provide this information for a host of reasons, however, device manufacturers can use this data to better utilize each tool depending on the level and the type of semiconductors they produce. Dirksen et al. first discussed the ring test as an effective method of determining lens aberrations in a step and repeat system, later in a scanning system. The method is based on two elements; the linear response to the ring test to aberrations and the use of multiple imaging conditions. The authors have been working to further enhance the capability on the test on the first small field 157 nm exposure system at International SEMATECH. This data was generated and analyzed through previously discussed methods for Z5 through Z25 and correlated back to PMI data. Since no 157nm interferemetric systems exist the lens system PMI data was collected at 248nm. Correlation studies have isolated the possible existence of birefringence in the lens systems via the 3-foil aberration which was not seen at 248nm. Imaging experiments have been conducted for various geometry's and structures for critical dimensions ranging from 0.13micrometers down to 0.10micrometers with binary and 0.07micrometers with alternating phase shift mask. The authors will review the results of these experiments and the correlation to imaging data and PMI data.
Deep-UV lithography using 248 and 193-nm light will be the imaging technology of choice for the manufacturing of advanced memory and logic devices for the next decade. The extension of 248nm technology to 0.150 micrometers and beyond has been accelerated with techniques, such as, Off Axis Illuminaton (OAI), Optical Proximity Correction (OPC) and Phase Shift Masks (PSM). Rapid development of such enhancements could provide a viable solution for the 0.13micrometers node. This continuous reduction of k1 to near 1/2 wavelength has intensified and issues related to Mask Error Factor (MEEF) have become a concern. Mask Error Factor, a phenomenon first discussed by Maurer et al., is defined as the CD Error at wafer level divided by the CD error at the reticle level multiplied by the lens magnification. The authors have been focusing on several key issues related to this high MEEF at various duty cycles. First, is the impact of MEEF across the entire exposure field for sub-0.15 micrometers imaging with KrF imaging. Secondly, the authors will discuss the coorelation between MEEF through pitch vs critical dimension with respect to partial coherence for bright and dark field imaging. Finally, the process window must be 'corrected' to account for across plate CD variation once the Mask Error Factor for a given critical dimension, pitch, reticle type, illumination condition and photoresist are determined. The authors will address the use of this new metric that can also assist in the specification of reticle CD's. Furthermore, we will address the various imaging solutions, briefly discussing how improvements in photoresist technology can assist and their impact on darkfield and lightfield imaging.
The exposure tool is a critical enabler to continue improving the packing density and transistor speed in the semiconductor industry. In addition to increasing resolution (improving packing density), a scanner is expected to provide tight linewidth control across the chip, ACLV (transistor speed). An important component of ACLV is lens aberrations. Recently techniques that allow the measurement in-situ of aberrations using Zernike coefficients have become available. We have measured the first 25 Zernike coefficients in two ASML PAS 500/700D DUV Step & Scan systems. The measured Zernikes are in agreement with PMI (Phase Measurement Interferometry) data collected at the lens manufacturer within 3.8 nm or less. We find good agreement between the variation of the Z5 (first order astigmatism) coefficient and the optimum focus offset between horizontal and vertical lines measured using FOCAL. There is also good agreement between Z5 and the linewidth difference between 160 nm horizontal and vertical lines with a 330 nm pitch. The lines were printed using an NA equals 0.68, (sigma) equals 0.70 on 3,800 angstrom of resist on top of an inorganic BARC. We find good correlation between the Z7 coefficient (first order coma) and linewidth variation across the slit. We also found that the effect of the aberrations as measured by linewidth range is a function of pitch. Linewidth range decreases as the duty ratio increases, reaching a minimum at a duty ratio of 1:1.44, and then increases again as the lines become isolated. This is surprising because these intermediate pitches also have the smallest focus-exposure window. We conclude that knowing the Zernike coefficients provides us with a very powerful tool to characterize our exposure tools. However to fully realize the benefit of this new tool we must improve the accuracy of our simulation tools.
The clearing dose, E0 is a commonly used parameter for measuring lithography process stability. Unfortunately, it is often difficult to accurately determine E0 utilizing the common technique of visual inspection. In this work, we outline an automated technique for the determination of E0 that is suitable for the volume manufacturing environment. This technique takes advantage of the ability of currently available automated film thickness metrology tools to take a large volume of resist thickness data over a range of exposure energies. The resulting contrast curve is then sliced to isolate the linear region, regressed, and extrapolated to generate a value for E0 that is suitable for use in process control. This algorithm is reduced to computer code and tuned for optimum performance. Regression statistics indicate that this type of fit is quite robust, with R2 values typically in excess of 0.95. Capability studies show the repeatability of this method to be far superior to traditional techniques, with single wafer reproducibility well below 1mJ/cm2. This improved method for the determination of E0 enjoys the benefits of accuracy and automation as compared to traditional visual methods. In addition to presenting the technique described above, we show the correlation of the new technique with induced process 'drifts,' thereby demonstrating its usefulness as a process monitor.
The application of optical enhancement techniques on high numerical aperture i-line steppers along with attenuated phase shift reticles have enabled contact processing to 0.35 micrometers and below. Previous work has shown that a high numerical aperture and low partial coherence improve contact printing capabilities. This paper focuses on a detailed evaluation of the effect of partial coherence on subhalf micron contact performance using both attenuated phase shift and binary reticles. The initial characterization of contact performance for contact sizes ranging from 0.3 micrometers to 0.45 micrometers confirms previous results that a 10% attenuated phase-shift provides the largest focus latitude when compared with a 6% attenuated reticle and a binary reticle. In extending previous work to 0.3 micrometers , it was confirmed that a larger focus latitude is achieved for a reduced partial coherence and high numerical aperture. Cross section micrographs presented confirm the improvement in profile and focus latitude by reducing the partial coherence. Cross section micrographs also demonstrate the capability with attenuated phase-shift to print 0.3 micrometers contacts at a pitch of 2.5 times the contact width. The pitch does not effect the contact focus latitude until it falls below 2.5 times the contact width. Uniformity (3(sigma) ) across the exposure field is reduced from 0.035 micrometers to 0.021 micrometers as the partial coherence is reduced from 0.6 to 0.3. The uniformity (3(sigma) ) across the wafer is reduced from 0.056 micrometers to 0.023 micrometers for the same reduction in partial coherence. Application of the best case process conditions also produced a focus latitude of 0.75 micrometers for 0.25 micrometers contacts. The results of this study show that i-line processing can be extended to 0.3 micrometers contact processing on random logic devices.
The manufacturing of high performance integrated circuits requires tight control of critical dimensions (CD) at poly pattern. Achieving these CD requirements forces process engineers to eliminate linewidth variation caused by reflective notching and thin film effects. Implementation of a bottom antireflective coating (BARC) can reduce or eliminate linewidth variations caused by reflective notching and thin film effects. With the additional process complexity, a number of issues must be resolved to obtain the true benefits of using a BARC material. The following paper discusses the characterization of a commercially available BARC material for 0.35 micrometers i-line poly patterning. Initial characterization of gratings and isolated lines on flat poly test wafers shows the resist process with BARC to have equal and in some cases better process capability compared to a conventional resist process. An 800 angstrom BARC film thickness on flat silicon wafers reduces the amplitude of the resist swing curve by 75%. On topography wafers an 800 angstrom BARC thickness eliminates reflective notching although for some small feature sizes, thin film effects still cause linewidth nonuniformity. Evaluations of BARC thicknesses ranging from 800 angstrom to 2,400 angstrom demonstrate the capability of the BARC to eliminate the swing effect in the resist by optimization of the BARC thickness. Cross sections of the resist profiles before and after etch demonstrate the ability for a repeatable pattern transfer. Wafer-to-wafer data and lot- to-lot data show the successful development of an etch process with a 0.03 micrometers bias. The data presented demonstrates the implementation of an optimized BARC process enhances the CD control capability at poly patterning for 0.35 micrometers i-line processing.
Extending i-line lithography to 0.35 micrometers processing is a realistic possibility because of improvements in photoresists, steppers, track equipment, and reticle technology. The manufacturing of 0.35 micrometers devices can include as many as twenty lithography levels, however, most of the critical issues can be addressed in printing the gate and contact levels. The optimized process for 0.35$ mum gates and contacts is presented in this paper. Even with advanced photoresists, enhancement techniques were needed to meet the processing requirements for these two levels on actual topography. The enhancement techniques used for the gate level were a TARC and modified illumination. A TARC was required to improve linewidth uniformity, and modified illumination to improve focus budget and exposure latitude. For contacts, attenuated phase shift was required to achieve workable focus latitude. The data presented shows that an optimized i-line resist processes with enhancement techniques can meet the requirements of volume production of 0.35 micrometers devices.
Evaluation of contact holes ranging from 0.35 micrometers to 0.7 micrometers for a number of i-line photoresists and attenuated phase-shift reticles has been completed. The study compared the effects of different photoresists patterned with a binary reticle as well as attenuated phase-shift reticles having transmission levels of 6%, 8%, and 12%. The measures of contact performance used to compare resist/reticles are focus budget, exposure latitude, and resolution. From the data collected, a large process window for sub half-micron contacts is demonstrated by using an optimum resist/reticle combination. With phase-shift, an increase in focus budget is realized with the amount of improvement dependent on the resist and transmission of the reticle. The resolution capability of all of the resists is improved by using phase-shift, although, phase-shift did not affect the linearity of the resists. Data collected points to the importance of optimizing the resist process with transmission level and applying the proper bias to maximize the focus budget.
Phase shift has been seen by many as a route to increase the resolution capability of optical microlithography beyond the Rayleigh criterion. The initial enthusiasm with which this technology was greeted has been moderated by the realization that prior to its practical application many technical challenges must be overcome. Nevertheless progress has been made. The question to be answered is no longer whether phase shift works, but rather which phase-shift approach and manufacturing technique provide the best practical solutions. We compare three techniques to build alternating phase-shift reticles: (1) deposited spin-on glass (SOG), (2) chemical vapor deposition (CVD) silicon dioxide, and (3) etched quartz. The merits of each approach are judged in terms of lithographic performance, ease of manufacture, and reliability. We condude that the SOG approach offers the best short-term solution to the manufacture of alternating phase-shift masks, although its lithographic performance is somewhat inferior to the other two and its long-term reliability remains to be determined. For deposited oxide to be a viable long-term approach, the oxide must be deposited under the chrome; for etched quartz, the roughness and defect density must be controlled.
The advantages of surface-imaging photoresist processes have been well documented in the literature: greater resolution, wider focus budget, and less sensitivity to topography and reflections from the substrate. The diffusion enhanced silylated resist (DESIRE) is a good example of a surface-imaging process. In previous papers we have presented characterization data for this process, and discussed some of the issues involved in its implementation in a manufacturing environment. More recently we have reviewed integration issues evolving from the interactions between the equipment, materials, and process. In this paper we continue our discussion of process integration issues focusing on: (1) electrical discharge, or arcing, during dry-development, and (2) line-width uniformity. Arcing is a very serious problem because of its catastrophic effect on yield. Thus far we have determined that the substrate and equipment influence the occurrence of arching, but further work remains to be done to determine all the possible causes. In previous papers we showed that the linewidth can be controlled across the wafer, and from wafer-to-wafer. By optimizing the magnetic field uniformity in our initial process set up, we were able to control the linewidth to within +/- 8% for 0.63 micrometers lines. However, to maintain this control over time, modifications in the silylation reactor had to be made. Additional improvements in the linewidth uniformity require us to go back and make modifications to the dry-develop reactor to improve the magnetic field uniformity further. These two examples illustrate the need to take a comprehensive or process integration approach to successfully implement this process.
Phase shift technology shows promise to extend the useful resolution and focus latitude to contemporary optical steppers. If successful in application, this represents significant cost savings to the manufacturing wafer fobs provided that the steppers can be used or modified to take advantage of phase-shift techniques. In this paper we explore the limits of phase-shift lithography, particularly at i-line. We do this following a two-fold approach: a) using simulations and b) collecting experimental data using different resist processes and phase-shift techniques. We conclude that using state-of-the-art photoresist processes and phase-shift techniques, i-line optical lithography can be extended to the 0.25 ?m regime.
The manufacturing of the next generation of DRAMs will require microlithographic capability in the 0.5 micrometers range. Our goal is to develop this capability using g-line optical microlithography; and i- line when g-line fails. To determine if surface-imaging is a viable alternative to extend the practical resolution limit of g-line lithography in a manufacturing environment, we have set up and characterized DESIRE, a surface-imaging process, in a high-volume DRAM manufacturing production line. This characterization study includes: (a) determination of basic lithographic data, (b) measurement of linewidth as the criterion to determine the stability of the process over time, (c) pattern transfer and stability of the resist to dry-etch processes, (d) measurement of any radiation-induced damage taking place during dry- development.
This paper describes a study of the silylation characteristics of different resists that are suitable for
single-layer, surface-imaging patterning applications. In particular, the effect of different process
parameters on the silicon diffusion in UCB's Plasmask®resist is discussed. The diffusion profile
of silicon in the resist is decorated by a staining technique followed by SEM analysis. This allows
for two-dimensional resolution of the diffusion profiles and the observation of other process
attributes. Links are established among exposure, silylation and etch by observing silylated profiles.
It is shown that the silylation profile characteristics are dominated by the resist image created during
exposure. Also, the effects of post-exposure bake and silylating agent temperature are presented.
Diffusion profiles for MacDermid's PR1024 are also shown.
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