Extreme ultraviolet (EUV) materials are deemed as critical to enable and extend the EUV lithography technology. Currently both chemically amplified resist (CAR) and metal-oxide resist (MOR) platforms are candidates to print tight features on wafer, however patterning requirements, process tonality (positive or negative), illumination settings and reticle tonality (dark or bright) play a fundamental role on the material performance and in consequence on the material choice.
In this work we focus on the patterning of staggered pillars using a single EUV exposure, and this by looking at the lithographic and etching performance of CAR and MOR platforms, using metrics as process window, local critical dimension uniformity (LCDU), pillar edge roughness (PER), pillar placement error (PPE) and (stochastic) nano-failures.
As a bright field reticle shows a lower aerial image contrast to print pillars compared to the aerial image of contact holes using a dark field reticle, we also investigate alternative patterning solutions such as the tone reversal process (TRP) to pattern pillars from contact holes.
Introduction and problem statement
Given that EUV lithography allows printing smaller Critical Dimension (CD) features, it can result in non-normal distributed CD populations on ADI wafers [Civay SPIE AL 2014], leading to errors in predicted failure rates [Bristol SPIE AL 2017]. As a result, there is a need to quantify the actual behavior of the CD population extremes by means of massive metrology [Dillen EUVL 2018]. Not only allows this to study the CD distribution, we can in parallel also evaluate pattern quality and the failure mechanisms leading to defects. This massive metrology method provides an accurate failure rate based on CD, and enables new possibilities to define a failure rate based on different metrics in a single measurement.
We analyze the CD uniformity of pillars in polar coordinates using a global waveform based thresholding strategy. In conjunction with this CD information, we also evaluated the print quality of each individual measured feature.
Fig 1. In line detected anomalies and failure definitions
As we gather this information during the measurement of CD, we can limit the additional measurement overhead to neglectable levels.
Application and outlook
We will show how we can leverage this to determine a defect based process window and relations of failure mechanisms through process conditions (see figure 2). When we take failures in a CH dataset into account, we illustrate the effect on the shape of a large dataset distribution in figure 3.
Fig 2. Defect identification for a through exposure dose experiment of pillars. For each condition >13k pillars where measured. The plot clearly shows an asymmetric behavior due to different failure mechanisms at low and high energy. The 2 vertical lines at relative energies 0.93 and 1.05 times nominal indicate the low defect process window.
Fig 3. A distribution of measured regular grid dense CH. The red line is the unfiltered CD data, the blue line is the shape of the distribution after filtering individual CH measurements that have a much lower contrast than expected.
Illumination source optimization is a very fundamental task in wafer lithography. By optimizing the incidence angles at the reticle, the combined diffraction behavior of mask and projection optics can be modified. One of the most critical parameter to control in EUV lithography is contrast at best and through focus as this drives the stochastic effects. In this work, we will look at the illumination source optimization for staggered CH and pillars for DRAM applications driven by fundamental considerations at diffraction level.
LCDU (Local Critical Dimension Uniformity) is one of the biggest challenges in EUV lithography as well as throughput. High contrast illumination, so called, leaf hexapole illumination is proposed for staggered contact-hole array pattern. Leaf hexapole illumination shows much better LCDU compared with traditional hexapole illumination which has been used in DUV lithography so far. Stochastic noise model which was developed based on the particle nature of photon is updated to supplement a missing term. Model prediction is well matched with experimental results in wide range of wafer CD and mask CD. Further optimization of LCDU and/or dose-to-size can be predicted through mask CD optimization. By using illumination optimization and mask CD optimization technique, EUV single exposure process can be applied below D1z node or beyond.
As we presented in the last conference, it is much difficult to get down the k1 limit of EUV lithography compared to that of optical lithography especially recent immersion lithography. Even though current 0.33NA NXE3300 tool has enhanced aberration characteristics and variable illumination mode than its predecessor, ADT and NXE3100, still there are limitations related with resolution capability of EUV lithography. First of all, photon shot noise and immature resist performances play an important role in patterning of very fine patterns. As already known, low sensitivity resists have been widely used to reduce shot noise. However, when considering productivity in EUV lithography, high sensitivity resists are inevitable, so it is necessary to increase image contrast by reducing scanner blur like aberration, M3D, stray light et al. We have investigated the impact of aberration and limitation in illumination pupil fill ratio in EUV. In particular, the aberration sensitivity is different by the illumination conditions, this was intensified when using the particular pupil. Because the lens calibration is conducted with standard illumination condition in NXE3300, it is necessary to consider different aberration sensitivity in accordance with pattern and used pupil condition in EUV lithography. To ensure the process margin of tech node close to limit, a flexpupil with low pupil fill ratio (PFR) than 0.2 were required. Hence in order to avoid through-put loss at this condition, the new concept of the illuminator design is required without light loss. Contamination of collector mirror can affect the patterning also. We will also report about the patterning effect of pupil deformation by degraded collector in low PFR condition.
Sub 0.3k1 regime has been widely adopted for high volume manufacturing (HVM) of optical lithography due to various resolution enhancement technologies (RETs). It is not certain when such low k1 is feasible in EUV, though most technologies are available in EUV also. In this paper, experimental results on patterning performance of line space (L/S) and contact hole (C/H) in EUV lithography will be presented. First, practical k1 value with 0.33NA EUV lithography was investigated through experiment using NXE3300 EUV tool. Patterning limit, as defined by local critical dimension uniformity (LCDU) for C/H array pattern were measured with respect to various design rules. It was evaluated that the effect of off axis illumination (OAI) mode with various illumination conditions to improve the patterning performance and to reduce k1 limit. Then the experimental results of LCDU were compared with normalized image log slope (NILS) values from simulation. EUV source mask optimization (SMO) technologies to increase NILS with FlexPupil option of EUV scanner were evaluated and possibility of further improvement was also discussed.
Extreme Ultraviolet (EUV) is the most promising technology as substitute for multiple patterning based on ArF immersion lithography. If enough productivity can be accomplished, EUV will take main role in the chip manufacturing. Since the introduction of NXE3300, many significant results have been achieved in source power and availability, but lots of improvements are still required in various aspects for the implementation of EUV lithography on high volume manufacturing. Among them, it is especially important to attain high sensitivity resist without degrading other resolution performance. In this paper, performances of various resists were evaluated with real device patterns on NXE3300 scanner and technical progress of up-to-date EUV resists will be shown by comparing with the performance of their predecessors. Finally the prospect of overcoming the triangular trade-off between sensitivity, resolution, line edge roughness (LER) and achieving high volume manufacturing will be discussed.
The improvement of overlay control in extreme ultra-violet (EUV) lithography is one of critical issues for successful mass production by using it. Especially it is important to improve the mix and match overlay or matched machine overlay (MMO) between EUV and ArF immersion tool, because EUV process will be applied to specific layers that have more competitive cost edge against ArF immersion multiple patterning with the early mass productivity of EUVL. Therefore it is necessary to consider the EUV overlay target with comparing the overlay specification of double patterning technology (DPT) and spacer patterning technology (SPT). This paper will discuss about required overlay controllability and current performance of EUV, and challenges for future improvement.
Stochastic noise has strong impact on local variability such as LWR (Line Width Roughness), LCDU (Local Critical Dimension Uniformity) and LPE (Local Placement Error), and it is basically originated from the particle nature of photon. Statistical uncertainties of particles, same as the stochastic noises, can be analytically calculated by considering aerial image as a probability density function of photons. Contact-hole is the best pattern for counting its photon, so LCDU of contact-hole array is estimated and compared with experimental results. Among several possible statistical events from mask to resist pattern, three independent events of aerial image formation, photon absorption in resist, and chemical reaction including acid generation are considered to predict stochastic noise for both EUV (Extreme Ultra Violet) and ArF immersion lithography.
As EUV reaches high volume manufacturing, scanner source power and reticle defectivity attract a lot of attention. Keeping a EUV mask clean after mask production is as essential as producing a clean EUV mask. Even though EUV pellicle is actively investigated, we might expose EUV masks without EUV pellicle for some time. To keep clean EUV mask under pellicle-less lithography, EUV scanner cleanliness needs to meet the requirement of high volume manufacturing. In this paper, we will show the cleanliness of EUV scanners in view of mask particle adders during scanner exposure. From this we will find several tendencies of mask particle adders depending on mask environment in scanner. Further we can categorize mask particle adders, which could show the possible causes of particle adders during exposure in scanners.
In this paper, we will present the experimental comparison results on contact holes (CHs) and pillars patterning in EUV lithography with several candidate processes. Firstly, we have compared the normalized image log-slope (NILS), local critical dimension uniformity (LCDU) and dose-to-size (DtS) with respect to positive tone imaging (PTI) and negative tone imaging (NTI) process by EUV stochastic simulation. From the simulation results, we found that NTI process has higher absorbed photon density that can reduce the DtS and the LCDU of pillars pattern is improved with higher NILS compared to CHs patterning with similar DtS. So we have experimentally evaluated the pillars patterning process with 0.25NA EUV scanner system and compared the process margin, LCDU and DtS with the same parameters of the CHs pattering process. Further, we have demonstrated the CHs patterning with reverse process from pillars by using the dry development rinse process (DDRP). Different to the simulation results, the experimental LCDU results of pillars pattern and CHs pattern by DDRP show worse values comparing with the reference resist CHs pattern. In order to analyze these results, we have investigated the effect of flare, target CD, PR thickness and mask stack of the experimental conditions. Furthermore, we have evaluated the pillar patterning with NTD resist and by DDRP.
Experimental local CD uniformity (LCDU) of the dense contact-hole (CH) array pattern is statistically decomposed into stochastic noise, mask component, and metrology factor. Each component are compared quantitatively, and traced after etching to find how much improvement can be achieved by smoothing. Etch CDU gain factor is defined as the differential of etch CD by resist CD, and used to estimate etch CDU on resist CDU. Stochastic noise has influenced on not only LCDU but also local placement error (LPE) of each contact-hole. This LPE is also decomposed into its constituents in the same statistical way. As a result, stochastic noise is found to be the most dominant factor on LCDU and LPE. Etch LCDU is well expected by Etch Gain factor, but LPE seems to be kept same after etching. Fingerprints are derived from the repeating component and the boundary size for excluding proximity effect in analysis is investigated.
EUV lithography (EUVL) is the most promising technology to extend the resolution limit, and is expected to be used if the enough source power is delivered and mask defect mitigation method is developed. However, even in that case, the number of EUV steps will be restricted by its high cost, and ArF immersion will still take a major role in the chip manufacturing. Therefore, it is important to check and improve the mix-match overlay (MMO) between EUV and ArF immersion steps. In this paper, we evaluate EUV MMO with ArF immersion system by comparing with dedicated chuck overlay (DCO). The major contributors on MMO are random and field component from overlay analysis. MMO is expected to be below 3nm by applying 18para CPETM(correction per exposure) and RegCTM(Registraion error correction). We consider High oder CPETM need to be developed for further improvement.
193 nm inspection for various defect types on top of the extreme-ultraviolet (EUV) mask is studied. The antireflection coating (ARC) is tried to enhance the defect inspection. However, adding ARC is not helpful to increase the sensitivity. Thus, 2 nm TaBO generally used for preventing the oxidation is mainly used. The aerial image deformation caused by the defect is compared to that of the defect free mask. Peak intensity difference is quantized and the sensitivity that is comparable to the ITRS defect inspection limit is chosen. The inspection criterion for typical defect types of extrusion, intrusion, pindot and pinhole is compared.
As design rule of semiconductor decreases continuously, overlay error control gets more and more important and challenging. It is also true that On Product Overlay (OPO) of leading edge memory device shows unprecedented level of accuracy, owing to the development of precision optics, mechanic stage and alignment system with active compensation method. However, the heating of reticle and lens acts as a dominant detriment against further improvement of overlay. Reticle heating is more critical than lens heating in current advanced scanners because lens heating can be mostly compensated by feed-forward control algorithm. In recent years, the tools and technical ideas for reticle heating control are proposed and thought to reduce the reticle heating effect. Nevertheless, it is not still simple to predict the accurate heating amount and overlay. And it is required to investigate the parameters affecting reticle heating quantitatively. In this paper, the reticle pattern density and exposure dose are considered as the main contributors, and the effects are investigated through experiments. Mask set of various transmittance are prepared by changing pattern density. After exposure with various doses, overlay are measured and analyzed by comparing with reference marks exposed in heating free condition. As a result, it is discovered that even in the case of low dose and high transmittance, reticle heating is hardly avoidable. It is also shown that there is a simple relationship among reticle heating, transmittance and exposure dose. Based on this relationship, the reticle heating is thought to be predicted if the transmittance and dose are fixed.
Improving Critical Dimension Uniformity (CDU) for spacer double patterning features is a high priority for double
patterning technology. In spacer double patterning the gaps between the spacers are established through various
processes (litho, etch, deposition) with different process fingerprints and the CDU improvement of these gaps requires an
improved control solution. Such a control solution is built upon two pillars: metrology and a control strategy.
In this paper Spacer Patterning Technology CDU control using an angle resolved scatterometry tool is evaluated. CD
results obtained with this scatterometer on CDU wafers are measured and the results are correlated with those from the
traditional CD-SEM. CD wafer fingerprints are compared before and after applying the advanced control strategy and
CDU improvements are reported. Based on the results it is concluded that scatterometry qualifies for a spacer process
CDU control loop in a manufacturing environment.
Intra-field CD uniformity control is one of hurdles in EUV lithography. Reflection imaging system intrinsic to EUV
causes CD non-uniformity especially in exposure field edge. To analyze dominant contributors to make this intra-field
CD non-uniformity in EUV lithography, influence of flare from adjacent fields and in-band and out of band refection
from reticle masking blind(REMA) and mask black border were investigated through intensive sampling of CD
measurement. Also mask border condition and REMA open settings are split into various settings to find out the impacts
from each contributor. Two ASML EUV scanners, alpha demo tool(ADT) and pre-production tool(PPT) are used for the
experiment. Fortunately, DUV out of band(OoB), reflection of REMA and the flare from adjacent fields are found to be
not significant in NXE3100. The results presented here lead us to the conclusion that the EUV refection from mask black
border is the main contributor and CD non-uniformity of the field edge can be overcome through optimized REMA
Extreme ultraviolet lithography is about to be realized in mass production even though there are many obstacles to be
overcome. Several years ago, the EUV pellicle was suggested by some people, but the idea of using the EUV pellicle
was abandoned by most people because there were big problems that were believed to be almost impossible to
overcome. The EUV pellicle should be made of an inorganic material instead of a common organic pellicle and should
be very thin due to EUV transmission. In addition to that the support of the very thin pellicle film should be used. The
structure of the support of the pellicle thin film should not make any noticeable intensity difference on the top of the
patterned mask side. However, the experimental result of the Intel showed the interference images with their suggested
support structure. In the Intel's report, the structure of the support was honeycomb or regular mesh type with a ~ 10 μm
line width and a ~100 μm pitch size. We study the intensity distributions on the top of mask for various combinations
around the above the mentioned scales and the support structures. The usable structure of the support will be reported
based on our simulation results, which would open the possibility of the EUV pellicle in mass production.
Typical overlay metrology marks like Box-in-Box or Advanced-Imaging-Marks print surprisingly poor when exposed
with extreme off-axis-illumination. This paper analyzes the root-cause for this behavior and establishes a method how to
understand and predict the results of overlay metrology on resist. A simulation flow is presented which covers the
lithographic exposure as well as the actual inspection of the resist profiles. This flow is then used to study the impact of
scanner/process imperfections on the overlay measurements; both image-based and diffraction-based overlay metrology
are covered. This helps to gain a deeper understanding of the critical parameters in the printing and inspection of overlay
marks, and eventually develop and assess mark enhancement strategies for image-based overlay metrology such as
chopping, or assess the benefit of diffraction-based overlay metrology. In parallel to the simulations, results of wafer
exposures are presented which investigate various aspects of overlay metrology and validate our simulations.
Overlay performance will be increasingly important for Spacer Patterning Technology (SPT) and Double Patterning
Technology (DPT) as various Resolution Enhancement Techniques are employed to extend the resolution limits of
lithography. Continuous shrinkage of devices makes overlay accuracy one of the most critical issues while overlay
performance is completely dependent on exposure tool.
Image Based Overlay (IBO) has been used as the mainstream metrology for overlay by the main memory IC companies,
but IBO is not suitable for some critical layers due to the poor Tool Induced Shift (TIS) values. Hence new overlay
metrology is required to improve the overlay measurement accuracy. Diffraction Based Overlay (DBO) is regarded to
be an alternative metrology to IBO for more accurate measurements and reduction of reading errors. Good overlay
performances of DBO have been reported in many articles. However applying DBO for SPT and DPT layers poses
extra challenges for target design. New vernier designs are considered for different DPT and SPT schemes to meet
overlay target in DBO system.
In this paper, we optimize the design of the DBO target and the performance of DBO to meet the overlay specification
of sub-3x nm devices which are using SPT and DPT processes. We show that the appropriate vernier design yields
excellent overlay performance in residual and TIS. The paper also demonstrated the effects of vernier structure on
overlay accuracy from SEM analysis.
Extreme Ultra-Violet (EUV) lithography is almost only solution reachable for next-generation lithography below 30nm
half pitch with relative cost competitiveness. In this study, we investigate the feasibility of EUV lithography for applying
2X nm dynamic random access memory (DRAM) patterning. Very short wavelength of 13.5nm adds much more
complexity to the lithography process. To understand for challenges of EUV lithography for high volume manufacturing
(HVM), we study some EUV specific issues by using EUV full-field scanners, alpha demo tool (ADT) at IMEC and pre-production
tool (PPT) at ASML. Good pattern fidelity of 2X nm node DRAM has been achieved by EUV ADT, such as
dense line and dense contact-hole. In this paper, we report on EUV PPT performance such as resolution limit, MEEF,
across slit CD uniformity (CDU) and focus & exposure latitude margin with 2X nm node DRAM layers in comparison
with ADT performance. Due to less flare and aberration of PPT, we have expected that PPT shows good performance.
EUV lithography is the leading candidate for sub-32nm half-pitch device manufacturing. EUV Pre-Production Tool
(PPT) is expected to be available at the end of 2010. As EUVL era comes closer, EUVL infrastructure has to get mature
including EUVL mask stack. To reduce HV CD bias which comes from shadowing effect, thin mask stack has been
considered. We presented that EUVL mask with 58nm absorber height shows same printing performance with
conventional EUVL mask with 80nm absorber height in our previous work. CD change and pattern damage at the
exposure field edges due to light leakage from the neighboring fields were also demonstrated.
In this paper, optimal mask stack which shows lower H-V CD bias than conventional structure using 70-nm-thick
absorber is proposed. To find minimized absorber height for sub-32nm pattering experimentally, printing result of
conventional mask and thin mask stack with 1:1 L/S patterns will be compared. Further-on, we demonstrate the printing
result of the reticle which is designed to minimize CD error at the exposure field edges due to mask black border
reflectivity by reducing reflectivity from the absorber.
All the wafers are exposed at ASML Alpha Demo Tool (ADT) and Pre-Production Tool (PPT) S-litho EUV is used for
Flare is hard to control only by hardware-wise means in EUV lithography. Therefore flare compensation through layout
correction is necessary. PSF is measured along various slit positions by using clearing resist pad with various sizes in
EUV Alpha Demo Tool (ADT) in IMEC. The measured PSF is compared to that derived from mathematically calculated
PSD modeling from surface roughness of the projection optics by suppliers. Degree of variation in flare level of real
device is measured experimentally with real device layout with clearing pads in it.
Flare is calculated as convolution of PSF (Point Spread Function) and pattern density. This requires astronomical amount
of computational time, because PSF in EUV has a very long tail that could even reach around several tens of thousands micron range. Therefore we investigated the pattern density of real devices with increasing radius of annulus. If the pattern densities in each annulus are saturated in some level, convolution integral with shorter range is sufficient and longer tail part of PSF can be approximated with fixed DC flare level dependent on saturated pattern density. Finally we discuss about the pending issues regarding flare correction for real devices application of EUV lithography.
Conventional EVUL mask has 80nm absorber height which brings considerable shadowing effect. H-V CD bias of 40nm
line and space by shadowing effect is more than 4nm, and that is expected to increase much more for narrower patterns
by simulation. However various reports have been presented on mask shadowing bias correction, experimental results
are not reliable to derive required mask bias correctly. Even more difficulty will arise when complex 2D structures are
taken into account. Therefore minimization of shadowing effect by reducing absorber thickness is desirable. To transfer
EUV lithography from experimental stage to HVM era, we need to find optimum absorber height of EUVL mask which
allows us less shadowing effect with minimum loss of process window.
In this paper, we present optimal absorber height of EUV mask which has been found in terms of shadowing effect and
process window by simulation and exposure. To find minimized absorber height experimentally, we will compare the
printing result of conventional and thin mask stack using simple 1:1 line and space and island patterns. Simulated H-V
CD bias and process window will be presented.
In this study, in order to accurately predict the shadowing and flare effect of EUVL, we compared
and analyzed the wafer and simulation result of the shadowing and flare effect of the EUV alpha demo tool at
IMEC. Flare distribution of the EUV Alpha Demo tool was measured and was used in simulation tool to
simulate several test case wafer result. Also, shadowing effect of the in-house created mask was measured
and compared with simulation result to match the predictability of the simulation tool.
Shadowing test comparison of wafer to simulation showed that simulation with resist model
showing better overall fitness to actual wafer result. Both aerial and resist model simulation result was within
2.33nm to wafer result. Measured wafer CD to simulation CD comparison for flare showed that average error
RMS of 3 test cases was 0.52, 2.05 and 3.47 nm for each test case respectively. In order to have higher
accuracy for flare simulation, larger diameter size for flare profile is necessary. Also from shadow test, resist
model better fit the wafer trend than using only the aerial image for simulating shadowing effect. EUV tool
showed very promising result for sub 30nm DRAM critical layer printing ability and with proper flare and
shadowing correction, reasonable result is expected for sub 30 and beyond critical layers of DRAM using
EUV lithography. Further work will be done to compensate flare and shadowing effect of EUV.
One of the major issues introduced by development of Extreme Ultra Violet Lithography (EUV) is high level of flare and shadowing introduced by the system. Effect of the high level flare degrades the aerial images and may introduce unbalanced Critical Dimension Uniformity (CDU) and so on. Also due to formation of the EUV tool, shadowing of the pattern is another concern added from EUVL. Shadowing of the pattern will cause CD variation for pattern directionality and position of the pattern along the slit. Therefore, in order to acquire high resolution wafer result, correction of the shadowing and flare effect is inevitable for EUV lithography.
In this study, we will analyze the effect of shadowing and flare effect of EUV alpha demo tool at IMEC. Simulation and wafer testing will be analyzed to characterize the effect of shadowing on angle and slit position of the pattern. Also, flare of EUV tool will be plotted using Kirk's disappearing pad method and flare to pattern density will also be analyzed. Additionally, initial investigation into actual sub 30nm Technology DRAM critical layer will be performed. Finally simulation to wafer result will be analyzed for both shadowing and flare effect of EUV tool.
In this paper, we will present comparison of DRAM cell patterning between ArF immersion and EUV lithography which
will be the main stream of DRAM lithography. Assuming that the limit of ArF immersion single patterning is around
40nm half pitch, EUV technology is positioned on essential stage because development stage of device manufacturer is
going down sub-40nm technology node. Currently lithography technology, in order to improve the limitation of ArF
immersion lithography, double patterning technology (DPT) and spacer patterning technology (SPT) have been
examined intensively. However, double patterning and spacer patterning technology are not cost-effective process
because of complexity of lithography process such as many hard mask stacks and iterative litho, etch process. Therefore,
lithography community is looking forward to improving maturity of EUVL technology.
In order to overcome several issues on EUV technology, many studies are needed for device application. EUV
technology is different characteristics with conventional optical lithography which are non-telecentricity and mask
topography effect on printing performance. The printed feature of EUV is shifted and biased on the wafer because of
oblique illumination of the mask. Consequently, target CD and pattern position are changed in accordance with pattern
direction, pattern type and slit position of target pattern.1
For this study, we make sub-40nm DRAM mask for ArF immersion and EUV lithography. ArF attenuated PSM (Phase
Shift Mask) and EUV mask (LTEM) are used for this experiment; those are made and developed by in-house captive
maskshop. Simulation and experiment with 1.35NA ArF immersion scanner and 0.25NA EUV full field scanner are
performed to characterize EUV lithography and to compare process margin of each DRAM cell. Two types of DRAM
cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node pattern with
contact hole shape. Line and space pattern is also studied through 24nm to 50nm half pitch for this experiment.
Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE and Solid-EUV are
also used in order to study characteristics of EUV patterning through rigorous EMF simulation. We also investigated
shadowing effect according to pattern shape and design rule respectively. We find that vertical to horizontal bias is
around 2nm on 32nm to 40nm half pitch line and space pattern. In the case of DRAM cell, we also find same result with
line and space pattern. In view of mask-making consideration, we optimize absorber etch process. So we acquire vertical
absorber profile and mask MTT(Mean To Target) within 10% of target CD through several pitch.
Process windows and mask error enhancement factors are measured with respect to several DRAM cell pattern. In the
case of one dimensional line and space and two dimensional brick wall pattern, vertical pattern shows the best
performance through various pitches because of lower shadowing effect than horizontal pattern. But in case of contact hole DRAM cell pattern such as storage node pattern, it has bigger MEF value than one or two dimensional pattern
because of independency of shadowing effect. Finally, we compare with 2x, 3x and 4x DRAM cell patterning
performance in terms of pattern fidelity, slit CD uniformity and shadowing effect.
In the field of lithography technology, EUV lithography can be a leading candidate for sub-30 nm technology node.
EUVL expose system has different characteristics compared to DUV exposure system. EUV source wavelength is short
and no material is transparent to the source. So off-axis reflective optic system is used for patterning in place of on-axis
refractive system of DUV system. And different reticle design is needed that consists of 40 pair of Mo/Si multi layer
and absorber layer in place of conventional mask. Because of the oblique incidence on the mask, shadowing effect is
occurred such as pattern asymmetry, shift and pattern bias depending on pattern orientation. For non-telecentric
characteristics of EUV scanner, shadowing effect produces CD variation versus field position. Besides, it is well
known that EUV scanner has bigger flare than conventional DUV scanner. Therefore, the correction of mask shadowing
effect and flare level are one of the important issues for EUV lithography.
In this paper, process window and MEF of EUV lithography has been examined by 3D mask simulation. CD
variation by shadowing is simulated for various pattern orientations. A shadowing correction method has been
calculated due to field position to reduce shadowing effect. And the correction effect is examined by simulation and
Experimental results. Principle of radial overlay shift due to field position is verified then the shift length of line and
space pattern is calculated.
As a design rule shrink down aggressively, various RETs (Resolution Enhancement Technology) have been
developed to extend the resolution limits of lithography. Until now, next generation lithography has been focused on
EUV technology. But no one can assure when EUV will be implemented. So, we must develop new technology with
current immersion tool to catch up with aggressive design rule. One of those is DPT (Double Patterning Technology),
however there are also many challenges to overcome such as patterning, overlay, hard mask etch and so on. The most
critical issue would be overlay, because it affects CD (Critical dimension) uniformity directly. Therefore, overlay
control is very important between 1st DP layer and 2nd DP layer. We utilized ArF immersion scanners for this experiment.
In this paper, DP process flow, hard mask film dependency, align method dependency, efforts of new align key design
and direct align analysis in DP overlay will be reported to understand and get better overlay accuracy than tool
specification. It is needed to be verified that how much they take an effect on improving the DP overlay. Continuously
we can conclude that most efforts in DPT should be focused on overlay control issue.
In this paper, we will present comparison of attenuated phase shift mask and binary intensity mask at hyper-NA
immersion scanner which has been the main stream of DRAM lithography. Some technical issues will be reported for
polarized illumination in hyper-NA imaging. One att.PSM (Phase Shift Mask) and three types of binary intensity mask
are used for this experiment; those are ArF att.PSM ( MoSi:Å ), thick Cr ( 1030Å ) BIM (Binary Intensity Mask),
thin Cr ( 590Å ) BIM and multi layer ( Cr:740Å / MoSi:930Å ) BIM. Simulation and experiment with 1.35NA
immersion scanner are performed to study influence of mask structure, process margin and effect of polarization. Two
types of DRAM cell patterns are studied; one is an isolation pattern with a brick wall shape and another is a storage node
pattern with contact hole shape. Line and space pattern is also studied through 38nm to 50nm half pitch for this
experiment. Lithography simulation is done by in-house tool based on diffused aerial image model. EM-SUITE is also
used in order to study the influence of mask structure and polarization effect through rigorous EMF simulation.
Transmission and polarization effects of zero and first diffraction order are simulated for both att.PSM and BIM. First
and zero diffraction order polarization are shown to be influenced by the structure of masking film. As pattern size on
mask decreases to the level of exposure wavelength, incident light will interact with mask pattern, and then transmittance
changes for mask structure. Optimum mask bias is one of the important factors for lithographic performance. In the case
of att.PSM, negative bias shows higher image contrast than positive one, but in case of binary intensity mask, positive
bias shows better performance than negative one. This is caused by balance of amplitude between first diffraction order
and zero diffraction order light.
Process windows and mask error enhancement factors are measured with respect to various design rules, i.e., different k1
levels at fixed NA. In the case of one dimensional line and space pattern, thick Cr BIM shows the best performance
through various pitches. But in case of two dimensional DRAM cell pattern, it is difficult to find out the advantage of
BIM for sub-45nm. It needs further study for two dimensional patterns. Finally, it was observed that thick Cr binary
intensity mask for sub-45nm has advantage for one dimensional line and space pattern.
ArF immersion lithography and RETs (Resolution Enhancement Technology) are the most promising technology for
sub 60nm patterning. As the device size shrinks, overlay accuracy has become more important due to small overlap
margin between layers. Overlay performance of immersion process is affected by thermal effect due to water evaporation,
so it shows worse performance than dry process and CD variation in DPT (Double Patterning Technology) process is
affected by overlay performance. So improvement of overlay accuracy became hot issue in realization of future
lithography technology, especially immersion process and double patterning process. Current status of lithography tool
shows 10 ~ 12nm (3sigma) overlay control in front-end process, but this overlay performance is not sufficient for
In this paper, we investigated the causes of overlay variation and tried to improve overlay accuracy in front-end process
of 60nm DRAM device. Therefore, the results in this study can be implemented to new technology such as immersion
and double patterning. First, overlay residual error factor is classified into two types, one is the equipment error factor
and the other is process error factor. Equipment error can be divided into SCMV (Single Chuck Mean Variation) by stage
accuracy variation, chuck to chuck mean and correction factor variation by using twin chuck etc. And process error can
be divided into alignment signal variation by chuck defocus (stage particle by contamination), increase of overlay
residual by material deposition, alignment key height variation by etch loading effect, overlay vernier attack by CMP
(Chemical Mechanical Polishing) process etc. We analyzed causes of these overlay error factor and we applied new
system and process to improve these overlay error factor.
In conclusion, we were able to find where overlay error comes from and how to improve overlay accuracy in 60nm
device, and we got good overlay performance using new alignment system and process optimization.
Though immersion lithography is on the verge of starting mass-production, demerit in overlay controllability by
immersion is thought as one of last huddle for that. The first issue in immersion tool has not been matured compared to
dry tool. As design rule is getting smaller, overlay specification is also changing the same way. But immersion tool is
not ready to meet this tighter overlay specification. The second issue is regarding the material which is used for
immersion process: top coat and water. Process details of material are needed to be verified thoroughly about how each
parameter affect on alignment and overlay respectively. In this paper, we made a split experiment about machine
parameter and investigated top coat effect on overlay. To improve overlay performance of immersion, we analyzed
machine parameters: scan-speed, settling time, UPW(Ultra Pure Water) flow etc. And we made an experiment about
how the effect of top coat is appeared on overlay through simulation and experiment. In the experiments, we used
ASML 1400i scanner. Resolution improvement of immersion tool has been proved by lots of papers, but it is need to be
verified of overlay controllability that getting tighter. Continuously, we believe that most efforts are to be focused on
overlay control issue.
Double patterning lithography has been one of the candidates for sub-40nm patterning era, and has a lot of process
issues to be confirmed. Last year, we presented the issues in double patterning lithography with a real flash gate pattern.
Process flow was suggested and CD uniformity due to overlay was analyzed. And the layout decomposition and the two
types of double patterning of positive and negative tone were studied with 1-dimensional pattern. In this paper, the
implementation to DRAM patterns is examined, which consist of 2-dimensional patterns. Double patterning methods and
the selection of their tone for each layer are studied, and the difficulties from the randomness of core pattern are also
considered. As a result, DRAM patterns have more restrictions on the double patterning method and selection of tone,
and the aggressive layout decomposition should be designed to solve the difficulty in core patterning. Therefore, 37nm
DRAM layout can be patterned and the overlay control and cost still remain as dominant obstacles.
In this paper, we will present experimental results on 45nm node patterning of DRAM and some technical issues for
polarized illumination in hyper NA imaging. First, practical k1 limit of 1.2NA ArF immersion system is investigated
through experiment. Process window and mask error enhancement factors are measured with respect to various design
rules, i.e., different k1 levels at fixed NA. Reasonable process window and MEEF value of around 3 are achieved in
DRAM gate and isolation layers at around 0.28 k1 regime. It is obvious that feasibility of this lowered k1 was realized
by the help of polarized illumination when we compared the results with that of 60nm patterning at 0.93NA tool -
corresponding k1 is 0.29 - without polarized illumination. Then consideration about degree of polarization state must
come next to the benefit of polarized illumination. Input polarization state is changed by birefringence of lens or mask
materials but it is very difficult to correlate the birefringence level and critical dimension of patterns experimentally.
Double exposing method was contrived to measure the effect of degree of polarization on DICD. And we also measure
the polarization dependent transmittance of light on mask by using 1.2NA immersion scanner. As a result, birefringence
and mask feature interaction with light seems not to be a serious issue for 45nm hyper NA polarized imaging.
Pattern collapse for line widths under 32 nm printed by extreme ultra-violet lithography (EUVL) is investigated by using commercial tools. Pattern collapse phenomenon occurs very often in actual process. Pattern collapse means that pattern is bending, peel-off, and break of the resist, thus it affects the production and yield of semiconductor. In this paper, we newly defined and investigated the critical aspect ratio. Pattern collapse happens if the critical aspect ratio is smaller than aspect ratio. Because EUV resist has smaller adhesive strength than currently available DUV and ArF resists, EUV resist easily collapse more easily than DUV resist does. This phenomenon is successfully modeled.
Recently, a new technology called double exposure lithography is emerging as new technology that extends lithography factor under 0.25. The need of this technology comes from the delay in maturity of EUV technology such as light source, reflective mask and optics, and resist. However, double exposure technology requires additional processes including two hard mask deposition steps, one more lithography patterning step and two hard mask etching steps. In addition, there would be several issues such as patterning on topology problems for the case of second patterning and complexity in etching process. In brief, the complex process of double exposure technology should be simplified for real device production.
In this paper, we will introduce novel double exposure technology that minimizes the number of process steps by using silicon containing BARC. Silicon BARC acts as BARC and hard mask at the same time in our double exposure process so the process step and cost can be reduced. During first exposure step, silicon containing BARC take a role of BARC for first resist patterning and then remaining pattern of silicon containing BARC acts as hard mask pattern for second patterning and etching. Using this simple and novel process, more economic way of double exposure technology can be available. In this paper, the issues and countermeasures for silicon containing BARC based double exposure technology will be reported.
Scanning Electron Microscope (SEM) has been typical methods for measuring CD of nanopatterns until ArF process was introduced. However in case of ArF process, this method has serious drawback such as shrinkage of organic material by the irradiation of high-energy electron beam. The optical scatterometry system is considered to be promising method for measuring CD due to no damage on organic materials. Sub-80nm node gate was selected because of its measurement stability. CD, profile and thickness are compared with those measured by CD-SEM, cress-section SEM. The correlation degree is shown as GOF, R2, and Profile. Based on merit of speed, easiness and accurate measurement, optical CD method has been applied to CD uniformity. CD uniformity measured by OCD was very similar to that measured by SEM on gate pattern. Based on this result, OCD was applied for the improvement of CD uniformity combined with ASML's does-mapper in technology. We investigated the variation of thickness of organic BARC over topology of various size line and space patterned poly-Si by OCD.
ArF lithography has shrunk photo resist patterns down to 60nm from 80nm with the help of various RETs (resolution enhancement technologies). Photo resist thickness also has been thinner than ever to increase image contrast and DoF margin and to avoid pattern collapse due to high aspect ratio. Etching process became more difficult and marginal by using thin resist patterning so that new BARC materials having high etching selectivity are required. Since amorphous carbon (a-C) and SiON have good etch selectivity between them, they can be used as hard mask materials for thin resist process. Lithographic alignment system usually uses the light of 400 to 700nm. In general a-C has certain level of light absorption in this wavelength range and the absorption coefficient increases with deposition temperature of a-C. Because a-C film is not suitably transparent to the alignment light, overlay control might get worsen as the thickness of a-Carbon film increased. In this paper, we will present the effect of the thickness of a-Carbon film on alignment signal strength, alignment accuracy and overlay control of various layers. Simulation of alignment signal is conducted and compared with experiment results. It is also studied whether the overlay control can be improved by changing the spectrum of alignment light or structural design of alignment marks. Improvements on alignment accuracy and overlay control are examined by lowering the extinction coefficient, k of a-Carbon film.
In conclusion, because photo resist only is not sufficient for a mask during etch step as the thickness decreased further, adoption of new hard mask is inevitable. It is the alignment trouble for a-Carbon that should be cleared before being named as a main stream of new hard mask.
There have been imposed quite incompatible requirements on lithographic simulation tool for OPC, that is it should be enough accurate and enough fast. Though diffused aerial image model (DAIM) has achieved these goals successfully, rapid transition of lithography into very low k1 and sub-resolution regime makes it very difficult to meet these goals without loss of any of speed or accuracy. In this paper we suggested new modeling method of resist process which is called heterogeneous diffusion of aerial image. First, various examples of CD discrepancy between experiment and simulation with DAIM are suggested. Then the theoretical background of new model is explained and finally CD prediction performance of new model is demonstrated in 60nm 0.29k1 patterning of real DRAM devices. Improved CD prediction capability of new model is observed in various critical patterning of DRAM.
Double patterning lithography is very fascinating way of lithography which is capable of pushing down the k1 limit below 0.25. By using double patterning lithography, we can delineate the pattern beyond resolution capability. Target pattern is decomposed into patterns within resolution capability and decomposed patterns are combined together through twice lithography and twice etch processes. Two ways, negative and positive, of doing double patterning process are contrived and studied experimentally. In this paper, various issues in double patterning lithography such as pattern decomposition, resist process on patterned topography, process window of 1/4 pitch patterning, and overlay dependent CD variation are studied on positive and negative tone double patterning respectively. Among various issues about double patterning, only the overlay controllability and productivity seemed to be dominated as visible obstacles so far.
Though speculation on immersion is ignited by the possibility in realization of hyper NA lithography system which will have NA> 1.0, it is thought that the immersion era might come earlier even in ≤1.0 NA regime because of great benefit in increasing DOF. On the other hand, questions are still laid on maturity or reliability issues such as lens contamination, bubble defects, overlay control and so forth. The main subject of this paper is how to find the appropriate time for introduction of immersion. Basic performance of immersion lithography in 80nm DRAM is compared with that of conventional dry lithography through experiment and simulation. Result of simulation is quite well matched with that of the experiment, and therefore we can investigate the limit of conventional dry lithography based on the simulation results.60nm node might be remained as a last regime for conventional dry lithography by virtue of polarized illumination, and we can expect the shoreline beyond there.
To accomplish minimizing feature size to sub 60nm, new light sources for photolithography are emerging, such as F2(157nm), and EUV(13nm). However, these new lithographic technologies have many problems to be solved for real device production. In case of F2 lithography, pellicle issue makes it difficult to use of F2 source in mass production. In case of EUV, light source and mask fabrication issues must be solved for real device application. For these reasons, instead of new light sources, extension of dry ArF lithography has been studied for sub 70nm device production by using Resolution Enhancement Technology (RET) such as using high NA tools, off axis illumination, and phase shift mask. Recently, a new technology called ArF immersion lithography is emerging as a next generation lithography. The first problem of this technology is contamination issues that come from the dissolution of contaminants from the photoresist to the immersion liquid. The second is optical problem that comes from the using hyper NA system. To solve these two problems, we have developed top antireflective coating (TARC) material. This TARC material can be coated on resist without damage to the resist property. In addition to, this TARC material is easily developable by conventional 2.38 wt% TMAH solution. The reflective index of this TARC is adjusted to 1.55, so it can act as an antireflective material. To this TARC material for immersion, quencher gradient resist process (QGRP) was applied also. As a result, we could improve resolution and process margin. However, some of resists showed defects that were generated by this TARC material and QGRP. To solve this defect problem, we introduced buffer function to the TARC material. Thanks to this buffer function, we could minimize defects of resist pattern in immersion lithography.
512Mbit DRAM with 70 nm design rule was tailored using 0.31k1 ArF lithography technologies. Of the critical mask layers, four pattern layouts were demonstrated: brick wall, line/space, contact and line/contact patterns. For the sake of cost reduction, the conventional technologies were used. Results has shown that SLR (Single-Layer Resist) process, half-tone PSM and the conventional illuminations had a potential of manufacturing 70 nm DRAM. However, it was found that brick wall patterns had asymmetrical shape and total CD uniformity was out of target raging 9.2 nm through 16.3 nm depending mask layouts. We prospect that higher contrast resist and more elaborate resist process will address these problems sooner or later. In case the immersion lithography is not ready around the right time, the feasibility of 0.29k1 ArF lithography was studied through simulation and test, which represented that 0.29k1 technologies were likely to be applied for the development of 60 nm DRAM with the aid of RETs (Resolution Enhancement Technologies) including customized illumination and new hard mask process.
More simple and cost-effective shrinkage techniques for contact hole (C/H) are required instead of conventional technologies such as thermal flow, RELACS, SAFIER and CONPEAT with the aggressive reduction in size of devices. We have developed a new method, Coating Assisted Shrinkage of Space (CASS) process. This process simply coats polymer over the patterned wafer. It doesn't need a bake and rinse step for shrinkage. Sub-100 nm C/H patterns were successfully defined after coating CASS material with good profile.
We have studied several factors having an effect on LER in terms of resist chemistry, resist process, CD-SEM metrology, numerical aperture and sigma settings of the exposure tool, and the mask pattern. LER is extracted from the developed resist profile. In ArF lithography process, development and rinse process is very critical because ArF resist is relatively hydrophobic compared to KrF resist. It causes heterogeneous interaction at interface of resist and aqueous solution (developer or deionized water). We improved roughness at contact hole pattern by the introduction of wetting process prior to development. Clear and homogeneous rinsing is also needed to remove scum and swelled resist generated at development step. On the other hand, the roughness of mask pattern is one of the important factors of LER on wafer. We confirmed that this global dislocation is a potent influence but local edge roughness of mask is insignificant to wafer LER. This dislocation of pattern is originated from the lack of shot accuracy in E-beam writer using variable shaped beam.
In this paper, we discuss feasibility of ArF chromeless mask (CLM) for sub-80nm era. Simulation and experiment are performed in terms of influence of quartz sidewall angle of CLM, process margin for 80nm DRAM cells, and mask polarity such as trench or mesa etc. Mask layouts are optimized through the use of resist patterning simulation for various critical layers of DRAM with trench and mesa type CLM, respectively. Lithography simulation is done by using in-house tool based on diffused aerial image model. SOLID-CTM is also using in order to study the influence of quartz sidewall angle and mask polarity. In the case of mask polarity, mesa type CLM is easier to make in the view of mask-making process, but in view of lithographic performance, trench type CLM is found to be better than mesa type. Quartz sidewall angle of CLM is one of the important factors for lithographic performance. The quartz sidewall angle of CLM gives severe impact on the lithographic performance. As quartz sidewall angle of CLM gets below 90 degrees, image quality, such as process window, aerial image contrast, are further degraded especially in the mesa type CLM. In addition, we also studied influence of phase error, transmittance error etc.
Various enhancement techniques such as alternating PSM, chrome-less phase lithography, double exposure, etc. have been considered as driving forces to lead the production k1 factor towards below 0.35. Among them, a layer specific optimization of illumination mode, so-called customized illumination technique receives deep attentions from lithographers recently. A new approach for illumination customization based on diffraction spectrum analysis is suggested in this paper. Illumination pupil is divided into various diffraction domains by comparing the similarity of the confined diffraction spectrum. Singular imaging property of individual diffraction domain makes it easier to build and understand the customized illumination shape. By comparing the goodness of image in each domain, it was possible to achieve the customized shape of illumination. With the help from this technique, it was found that the layout change would not gives the change in the shape of customized illumination mode.
As design rule shrinks down continuously, various technology have been developed to extend the resolution limits of lithography. One of those is Double Exposure Technology(DET). This paper is about not only resolution improvement but also Critical Dimension(CD) variation reduction with DET. As the design rule shrinks below 100nm, the core/peripheral area where we used to think we had sufficient margin is becoming the bottle neck for device fabrication. In this paper, in order to compare optimized single exposure (cell focus) and DET (cell, core/peripheral focus) for critical dimension uniformity(CDU) on cell and core/peripheral area, CDU was measured from wafer by use of simulation and measurement. Gate layer of DRAM device was used for the experiment. Exposure condition for the single exposure was set to crosspole and for DET, dipole and conventional respectively. Optical proximity correction(OPC) was done with in-house simulation tool on stiching area of the double exposure experiment. Same exposure tool and same process condition were used for each experiment and only the exposure condition was changed to compare local CDU, intra-field CDU, wafer CDU to find out how much CD variation can be reduced.
The purpose of this paper is to do the direct comparison of between the novel chrome-less phase shift mask (CLM), which is suggest by Chen et. al. recently, and attenuated phase shift mask which has been in the main stream of DRAM lithography. Our study is focused on the question of whether the CLM technology has a potential advantages compared with attenuated PSM, so as to substitute the position of it in 0.3 k1 lithography era of DRAM. Firstly, some basic characteristics of both masks are studied, that is intensity distribution of diffraction orders and optical proximity effect etc. And then mask layouts are optimized through the resist patterning simulation for various critical layers of DRAM with CLM and attenuated PSM, respectively. Resolution performances such as exposure latitude and DOF margin and mask error enhancing factor etc. are compared through the simulations and experiments. In addition, it is also studied in the point of mask manufacturing of CLM such as phase control issues, defect printability, mask polarity, and so forth.
The main object of this paper is to investigate the root cause of CD change by neighboring field observed in KrF scanner (max. 0.70NA) and to measure the amount of stray light from neighboring field precisely. Line widths of gate pattern are measured at the isolated and surrounded field and the amount of CD change by neighboring field is found to be proportional to the clear ratio of mask. By exposing with special configuration, it is found that the line width is linearly decreased as the dose of neighboring field increases. From this linear dependency on doses of neighboring field, it is clear that non-negligible amount of light is scattered out into the adjacent field. The amount of this stray light level coming from neighboring field is obtained quantitatively by synthetic analysis of above result and double exposure to mimic background DC light by flare. About 1.2% of stray light from outside of the field is observed at the slit position close to the boundary of neighboring field. Disappearing pad test is also performed to measure the flare from exposure of field itself. Finally, it is obtained the distribution of total stray light - nominal flare plus flare from adjacent field - and it is found to be existed around 0.7% deviation of stray light across the slit.
Optical proximity correction (OPC) is well known as a predominant method to overcome the proximity effect. However, it is not so simple to implement OPC in real process because of the difficulty in designing, manufacturing and inspecting the masks. Simple and practical methods of overcoming the optical proximity effects (OPE) in DRAM application are widely studied in this work. Simulation based layout optimization is effective for periodic cell patterns but establishment of some tolerable rules for circuit design needed for random periphery patterns. The characteristics of optical proximity effects are investigated in sub-quarter micron lithography as a function of various optical parameters such as numerical aperture, degree of partial coherence, and illumination type. It is also investigated the dependency of OPE on the resist kind, resist thickness, soft bake and post exposure bake temperatures as well as different substrates films.
The most critical issues for lithographers, resolution, depth of focus, exposure latitude and proximity effect, have been frequently discussed. In addition to those issues, lens aberration effects such as astigmatism, coma, field curvature and distortion have been emphasized in view of process stabilization. Deep UV lenses have undergone improvements in the field curvature, distortion, and other aberrations to the point that they can be implemented for near quarter micron patterning. KrF excimer laser stepper and scanner have made Deep UV technology as a practical choice for lithographers to develop their own DRAM processes. In order to adopt process development beyond the region of ultimate resolution limit, precise lens aberration analyses are necessary. KrF excimer laser stepper (NA equals 0.55), used for 0.18 micrometers design rule patterning, is examined. Several types of real device pattern, such as word and bit line, active, storage node, contact hole patterns, are tested under various illumination conditions (conventional, various partial coherence, off-axis illumination). These results are compared with simulation results.
Modified illumination scheme such as off-axis illumination or low partial coherence illumination in combination with phase shift mask is very reliable technique even to the manufacturing stage. In spite of its benefit of drastic improvements in resolution and depth of focus, it has several well known drawbacks. Those are pattern structure dependency, increased proximity effect and significant degradation of illumination power. Furthermore, several studies are reported about the distortion-like registration error between each illumination aperture while various apertures are mix-used. However, the origin of this distortion-like overlay errors is still uncertain and just considered as having some relationship with lens aberration probably, coma. In this study, we investigated the nonlinear character of the registration errors and try to find out the implicit relations of its to the lens aberration character through experiments and simulations.
The practical limits of i-line top surface imaging process using a novolak based photoresist were investigated dependent on exposure techniques such as conventional and off-axis illumination. Ultimately, quarter micron small geometry was clearly delineated and depth of focus (DOF) latitude of 1.5micrometers and 2.7micrometers was achieved respectively for 0.25micrometers and 0.30micrometers lines and spaces pattern by annular illumination of 0.50NA. To compensate proximity effect caused by pattern density, sub-resolution auxiliary pattern was firstly optimized for off- axis illumination of quadrapole and annular. As a result, critical dimension (CD) difference between dense and isolated pattern in 0.30micrometers reduced to half-level compared to that of non-auxiliary pattern. It was found that desilylation phenomenon was critically affected by the kind of photopolymer reacted with silicon source and molecular weight of silylation agent. Novolak based polymer maintained superior silylation durability to polyvinyl phenolic (PVP) resin. New silylation process concept which is dual silylation method was developed to utilize PVP's merits in the silylation process against desilylation. Dry development lithography of i-line was feasible to practical application of prototype 256 mega bit DRAM which demands 0.30micrometers patterning with a reproducibility.