For enabling better electrostatic control of short channel devices, gate-all-around (GAA) nanowire/nanosheet (NW/NS) field-effect transistors (FETs) may replace FinFET in 3nm logic technology node and beyond. Horizontally stacked NW/NS FETs are especially promising due to its excellent electrostatics, short channel control, increased active width, and gate length scaling. In order to enable further scaling of GAA FETs, imec has been developing forksheet (FS) FET as well as complementary FET (CFET).
For the manufacturing of FS and CFETs, there are several new challenges which require isotropic and selective etching. In this work, we have been developed chemical isotropic dry etching for the several key process steps along with the integration flow, including Si/SiGe superlattice fin reveal, dielectric wall formation, local SOI formation, SiGe cavity etch as well as the dielectric etchback for the inner spacer formation, dummy gate removal and SiGe selective etch for the Si channel release
Here, we report the measurement of the dielectric spacer etch process for nanowire and nanosheet FET processes. A previously described Nanowire Test Structure (NWTS) was used for this study.[1, 2, 3] This structure has alternating Si/Si1-xGex/…/Si multilayers. Subsequent to the selective etching of the Si1-xGex layers (cavity etch), a silicon nitride (SiN) dielectric layer was deposited on the NWTS. Here we report on the use of Mueller Matrix Spectroscopic Ellipsometry based Scatterometry (MMSE) to measure the thickness of the SiN dielectric layer after deposition and after trim etch steps. Four different amounts of trim etch were characterized.
KEYWORDS: Silicon, Fin field effect transistors, Gallium arsenide, Critical dimension metrology, Plasma, Field effect transistors, Etching, Line edge roughness, Line width roughness, Transistors
R&D on transistor fabrication and scaling for current and future technology nodes involves various 3D-device architectures like the established finFET (fin “Field Effect Transistor”), and newer architectures like GAA (Gate All Around) which may include VFET (vertical FET), CFET (complimentary FET), etc. These new architectures are being investigated as potential solutions to enable further CMOS area and performance scaling and continue Moore’s law. Typically node to node area scaling is achieved through pitch reduction of critical layers such as contacted poly pitch (CPP) and fin pitch in FEOL, and Mx pitch in the BEOL. For such advanced nodes, at the device level, the CPP reduction translates to a stronger drive for shorter gate length (Lg) and so, for improved electrostatics control (Ion, Ioff, Tinv, etc.). Integration schemes for such advanced 3D architectures must deliver excellent process control and uniformity, especially for critical device features such as gate length and channel dimensions, and demand self-aligned multi-patterning schemes to address edge-placement accuracy, overlay, multiple mask sets, etc. A frequently encountered etch step in such integration schemes is the trimming of Si features made of mono, polycrystalline, or amorphous Si. Some key applications are listed here: fin trimming for (1) lateral transport finFET and for (2) vertical transport VFET, (3) final gate trim for lateral transport finFET, GAA/CFET, etc. (4) amorphous gate mandrel trim for lateral transport FETs (multi-patterning).
The three-dimensional architectures for field effect transistors (FETs) with vertical stacking of Gate-all-Around Nanowires provide a pathway to increased device density and superior electrical performance. However, the transition from research into manufacturing will only be successful if their feature shape, critical dimensions, and associated electrical performance are repeatable across the integrated circuit, across the wafer, and among multiple wafers. Patterning process control for these structures will require significant advances in metrology. Two techniques that are potential candidates for this purpose are Mueller Matrix Spectroscopic Ellipsometry based Scatterometry (MMSEscatterometry) and Critical Dimension Small Angle X-Ray Scattering (CDSAXS). In this work, we highlight the characterization of the Nanowire Test Structures fabricated from patterned Si/SixGe1-x/Si/SixGe1-x/Si/SixGe1-x/Si structures using CDSAXS. Preliminary experimental data shows sensitivity to the selective etching of subsurface SixGe1- x. CDSAXS diffraction data provides information in reciprocal space about line shape and periodicity as well as the amount of subsurface etching. Side lobes in the Intensity vs. Qz (structure height) data are observed around Qz positions of around 0.15 nm-1 and 0.5 nm-1 and are at the same positions in the measured and the simulated data for different amounts of SixGe1-x etch in the Nanowire Test Structures. This demonstrates its ability for successful measurement of the critical dimensions and 3D profile of the Nanowire Test Structures, which can then be extended to monitor several key process steps for Nanowire/Nanosheet FET fabrication.
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