A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.
As future patterning processes reach the limit of lithographic printability, continuous innovation in mandrel trim or shrink strategies are required to reach sub-20 nm line-space patterning. Growing concerns of lithography defectivity, mask selectivity, line edge roughness (LER), line width roughness (LWR), and critical dimension uniformity (CDU) present significant challenges towards this goal. The authors compare various alternative mandrel trim strategies to highlight potential solutions and drawbacks towards enabling successful printing of mandrels used in extreme ultraviolet (EUV) multi-patterning schemes. Through this comparison, the authors demonstrate the challenges of maintaining adequate pattern transferability while keeping aspect ratio-driven line roughness and material selectivity under control. By process partitioning, the limitations of traditional lithography and etch trimming strategies are highlighted, suggesting the need for new methods of CD reduction after the pattern has been transferred. These new trimming methods offer flexibility in CD control without negatively impacting the mandrel profile and demonstrates better tunability across different material sets, allowing for evaluation of different mask and mandrel material combinations for downstream process optimization.
Emerging memory devices, such as MRAM, RRAM, and PCM, plays an important role in in-memory computation technology which can lead to significant acceleration for machine learning and AI applications.[1-3] The basic structure of these memory cell is simply a pillar made of a wide range of materials, however, the local CD uniformity (LCDU) of the pillars is especially crucial for these memory devices. The stringent LCDU requirement derives from either the intrinsic small resistance difference between the two memory states or the requirement for creating a large number of memory states within a small range of resistance. Apparently, the stochastic variation in physical dimension will correspond to the variation in resistance from cell to cell, which will affect the correct readout of the memory states and fail the device.
Because the “local” CDU in this context refers to the variation within the memory array, i.e. typically within several um, it is almost impossible to correct by utilizing existing advanced tools or process control techniques. In this work, we will demonstrate four promising options to address the stochastic effect in LCDU of pillars: a) adopting new resists, b) PTD and NTD shrink, c) DSA, d) cross-SADP. Fig. 1 shows the general approach to achieve better LCDU by printing larger CD at litho and shrink by post-litho processing.[4] Here we carefully characterize two shrinking techniques and its efficacy on LCDU improvement. Fig. 2 shows two alternative approaches, i.e. DSA and cross-SADP.[5] We will carefully explore these four approaches for LCDU improvement with thorough characterization and analysis. Subsequent pattern transfer and the retention of the LCDU improvement and cost/quality trade-off will also be discussed. Defectivity learning will also be discussed.
Lithographic and pitch-multiplying spacer technologies are widely used to shrink interconnect periodicity within critical layers. This places significant burden on overlay and CD uniformity of the subsequently patterned vias to physically contact and electrically connect critical layers to the rest of the integrated circuit in a nearly defect-free and perfectly-consistent manner. We are evaluating the combination of EUV and DSA patterning technologies to meet this challenge and enable future technology nodes. The contact hole guide pattern is fabricated atop bilayer hardmask material by single-exposure EUV, surface-modified with telechelic polymer brush materials, and finally shrunk/rectified using self-assembled, lamella-forming polystyrene-block-polymethylmethacrylate (PS-b-PMMA). The nascent via pattern is then blanket exposed by DUV light and the photolyzed PMMA is selectively rinsed away. Here we study the process performance of DSA pattern wet etch chemistry and subsequent dry etch pattern transfer into bilayer hardmask material using both metrology and electrical yield measurements as evaluation criteria. In particular, the choice of wet etch solvation strength selective towards PMMA was varied from moderate (isopropanol, IPA) to good (acetic acid, AAc). Due to the ability of AAC to solubilize all covalently-untethered PMMA, regardless of molecular weight, the resulting average CD is wider and its local distribution is more uniform. In contrast, IPA is only capable of rinsing away the smallest PMMA fragments, resulting in relatively tighter bounds about the preferable blanket UV dose, and a smaller average CD and less-uniform local CD distribution. These morphological differences are confirmed by cross-sectional transmission electron micrographs. Brightfield inspection and inline electrical testing are used to compare relative defectivity and yield, respectively, to assess the potential impact on device performance for processes utilizing either solvent.
The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). Functional electrical testable Via-Chain structure is fabricated to verify the integrity of the proposed method. Through the analysis of the observed failure modes, the process is further improved. By validating DSA for such an important patterning element as metal cut, the DSA maturity can be further advanced and hopefully move DSA closer to HVM adoption.
This paper presents a design and technology co-optimization (DTCO) study of metal cut formation in the sub-20-nmregime. We propose to form the cuts by applying grapho-epitaxial directed self-assembly. The construction of a DTCO flow is explained and results of a process variation analysis are presented. We examined two different DSA models and evaluated their performance and speed tradeoff. The applicability of each model type in DTCO is discussed and categorized.
As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect.
Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.
KEYWORDS: Etching, Critical dimension metrology, Metals, Directed self assembly, Oxides, Back end of line, Dielectrics, Scanning electron microscopy, Tin, Lithography
The progress of using DSA for metal cut to achieve sub-20nm tip-to-tip (t2t) critical dimension (CD) is reported. Small and uniform t2t CD is very challenging due to lithographic limitation but holds the key to backend-of-the-line (BEOL) scaling. An integration scheme is demonstrated that allows the combination of design flexibility and fine, rectified local CD uniformity (LCDU). The combined effect of LCDU and centroid jittering will be discussed and compared to a hole shrink process using atomic layer deposition and spacer formation. The learning from this case study can provide perspectives that may not have been investigated thoroughly in the past. By including more important elements during DSA process development, such as metal cut, the DSA maturit y can be further advanced and move DSA closer to HVM adoption.
Initial readiness of extreme ultraviolet (EUV) patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the “effective” k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Using a grafted polymer brush adhesion layer, we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush, and resist. We show printing of sub-36-nm pitch features with a good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight, and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
KEYWORDS: 3D modeling, Calibration, Data modeling, Optical lithography, Nanotechnology, Very large scale integration, System on a chip, Logic, Research facilities
Direct Optimization (DO) of a 3D DSA model is a more optimal approach to a DTCO study in terms of accuracy and speed compared to a Cahn Hilliard Equation solver. DO’s shorter run time (10X to 100X faster) and linear scaling makes it scalable to the area required for a DTCO study. However, the lack of temporal data output, as opposed to prior art, requires a new calibration method. The new method involves a specific set of calibration patterns. The calibration pattern’s design is extremely important when temporal data is absent to obtain robust model parameters. A model calibrated to a Hybrid DSA system with a set of device-relevant constructs indicates the effectiveness of using nontemporal data. Preliminary model prediction using programmed defects on chemo-epitaxy shows encouraging results and agree qualitatively well with theoretical predictions from a strong segregation theory.
In this study, the integrity and the benefits of the DSA shrink process were verified through a via-chain test structure, which was fabricated by either DSA or baseline litho/etch process for via layer formation while metal layer processes remain the same. The nearest distance between the vias in this test structure is below 60nm, therefore, the following process components were included: 1) lamella-forming BCP for forming self-aligned via (SAV), 2) EUV printed guiding pattern, and 3) PS-philic sidewall. The local CDU (LCDU) of minor axis was improved by 30% after DSA shrink process. We compared two DSA Via shrink processes and a DSA_Control process, in which guiding patterns (GP) were directly transferred to the bottom OPL without DSA shrink. The DSA_Control apparently resulted in larger CD, thus, showed much higher open current and shorted the dense via chains. The non-optimized DSA shrink process showed much broader current distribution than the improved DSA shrink process, which we attributed to distortion and dislocation of the vias and ineffective SAV. Furthermore, preliminary defectivity study of our latest DSA process showed that the primary defect mode is likely to be etch-related. The challenges, strategies applied to improve local CD uniformity and electrical current distribution, and potential adjustments were also discussed.
Metrology of nanoscale patterns poses multiple challenges that range from measurement noise, metrology errors, probe size etc. Optical Metrology has gained a lot of significance in the semiconductor industry due to its fast turn around and reliable accuracy, particularly to monitor in-line process variations. Apart from monitoring critical dimension, thickness of films, there are multiple parameters that can be extracted from Optical Metrology models3. Sidewall angles, material compositions etc., can also be modeled to acceptable accuracy. Line edge and Line Width roughness are much sought of metrology following critical dimension and its uniformity, although there has not been much development in them with optical metrology. Scanning Electron Microscopy is still used as a standard metrology technique for assessment of Line Edge and Line Width roughness. In this work we present an assessment of Optical Metrology and its ability to model roughness from a set of structures with intentional jogs to simulate both Line edge and Line width roughness at multiple amplitudes and frequencies. We also present multiple models to represent roughness and extract relevant parameters from Optical metrology. Another critical aspect of optical metrology setup is correlation of measurement to a complementary technique to calibrate models. In this work, we also present comparison of roughness parameters extracted and measured with variation of image processing conditions on a commercially available CD-SEM tool.
The progress of three potential DSA applications, i.e. fin formation, via shrink, and pillars, were reviewed in this paper. For fin application, in addition to pattern quality, other important considerations such as customization and design flexibility were discussed. An electrical viachain study verified the DSA rectification effect on CD distribution by showing a tighter current distribution compared to that derived from the guiding pattern direct transfer without using DSA. Finally, a structural demonstration of pillar formation highlights the importance of pattern transfer in retaining both the CD and local CDU improvement from DSA. The learning from these three case studies can provide perspectives that may not have been considered thoroughly in the past. By including more important elements during DSA process development, the DSA maturity can be further advanced and move DSA closer to HVM adoption.
Initial readiness of EUV patterning has been demonstrated at the 7-nm device node with the focus now shifting to driving the 'effective' k1 factor and enabling the second generation of EUV patterning. In current EUV lithography, photoresist thicknesses <30 nm are required to meet resolution targets and mitigate pattern collapse. Etch budgets necessitate the reduction of underlayer thickness as well. Typical spin-on underlayers show high defectivity when reducing thickness to match thinner resist. Inorganic deposited underlayers are lower in defectivity and can potentially enable ultrathin EUV patterning stacks. However, poor resist-inorganic underlayer adhesion severely limits their use. Existing adhesion promotion techniques are found to be either ineffective or negatively affect the etch budget. Here, using a grafted polymer brush adhesion layer we demonstrate an ultrathin EUV patterning stack comprised of inorganic underlayer, polymer brush and resist. We show printing of sub-36 nm pitch features with good lithography process window and low defectivity on various inorganic substrates, with significant improvement over existing adhesion promotion techniques. We systematically study the effect of brush composition, molecular weight and deposition time/temperature to optimize grafting and adhesion. We also show process feasibility and extendibility through pattern transfer from the resist into typical back end stacks.
Pattern transfer fidelity is always a major challenge for any lithography process and needs continuous improvement. Lithographic processes in semiconductor industry are primarily driven by optical imaging on photosensitive polymeric material (resists). Quality of pattern transfer can be assessed by quantifying multiple parameters such as, feature size uniformity (CD), placement, roughness, sidewall angles etc. Roughness in features primarily corresponds to variation of line edge or line width and has gained considerable significance, particularly due to shrinking feature sizes and variations of features in the same order. This has caused downstream processes (Etch (RIE), Chemical Mechanical Polish (CMP) etc.) to reconsider respective tolerance levels. A very important aspect of this work is relevance of roughness metrology from pattern formation at resist to subsequent processes, particularly electrical validity. A major drawback of current LER/LWR metric (sigma) is its lack of relevance across multiple downstream processes which effects material selection at various unit processes. In this work we present a comprehensive assessment of Line Edge and Line Width Roughness at multiple lithographic transfer processes. To simulate effect of roughness a pattern was designed with periodic jogs on the edges of lines with varying amplitudes and frequencies. There are numerous methodologies proposed to analyze roughness and in this work we apply them to programmed roughness structures to assess each technique’s sensitivity. This work also aims to identify a relevant methodology to quantify roughness with relevance across downstream processes.
Phase change material (PCM)-based memory cells have shown promise as an enabler for low power, high density memory. There is a current need to develop and improve patterning strategies to attain smaller device dimensions. In this work, two methods of patterning of PCM device structures was achieved using directed self-assembly (DSA) patterning: the formation of a high aspect ratio pore designed for atomic layer deposition (ALD) of etch damage-free PCM, and pillar formation by image reversal and plasma etch transfer into a PCM film. We show significant CD reduction (180 nm to 20 nm) of a lithographically defined hole by plasma etch shrink, DSA spin-coat and subsequent high selectivity pattern transfer. We then demonstrate structural fabrication of both DSA-defined SiN pores with ALD PCM and DSA-defined PCM pillars. Challenges to both pore and pillar fabrication are discussed.
We report a systematic study of the feasibility of using directed self-assembly (DSA) in real product design for 7-nm fin field effect transistor (FinFET) technology. We illustrate a design technology co-optimization (DTCO) methodology and two test cases applying both line/space type and via/cut type DSA processes. We cover the parts of DSA process flow and critical design constructs as well as a full chip capable computational lithography framework for DSA. By co-optimizing all process flow and product design constructs in a holistic way using a computational DTCO flow, we point out the feasibility of manufacturing using DSA in an advanced FinFET technology node and highlight the issues in the whole DSA ecosystem before we insert DSA into manufacturing.
Directed self-assembly (DSA) of block copolymers (BCPs) has become a promising patterning technique for 7nm node hole shrink process due to its material-controlled CD uniformity and process simplicity.[1] For such application, cylinder-forming BCP system has been extensively investigated compared to its counterpart, lamella-forming system, mainly because cylindrical BCPs will form multiple vias in non-circular guiding patterns (GPs), which is considered to be closer to technological needs.[2-5] This technological need to generate multiple DSA domains in a bar-shape GP originated from the resolution limit of lithography, i.e. those vias placed too close to each other will merge and short the circuit. In practice, multiple patterning and self-aligned via (SAV) processes have been implemented in semiconductor manufacturing to address this resolution issue.[6] The former approach separates one pattern layer with unresolvable dense features into several layers with resolvable features, while the latter approach simply utilizes the superposition of via bars and the pre-defined metal trench patterns in a thin hard mask layer to resolve individual vias, as illustrated in Fig 1 (upper). With proper design, using DSA to generate via bars with the SAV process could provide another approach to address the resolution issue.
In recent years major advancements have been made in the directed self-assembly (DSA) of block copolymers (BCP). DSA is now widely regarded as a leading complementary patterning technique for future node integrated circuit (IC) device manufacturing and is considered for the 7 nm node. One of the most straightforward approaches for implementation of DSA is via patterning by graphoepitaxy. In this approach, the guiding pattern dictates the location and pitch of the resulting hole structures while the material properties of the BCP control the feature size and uniformity. Tight pitches need to be available for a successful implementation of DSA for future node via patterning which requires DSA in small guiding pattern CDs. Here, we show strategies how to enable the desired CD shrink in these small guiding pattern vias by utilizing high χ block copolymers and/or controlling the surface properties of the template, i.e. sidewall and bottom affinity to the blocks.
Directed self-assembly (DSA) with block-copolymers (BCP) is a promising lithography extension technique to scale below 30nm pitch with 193i lithography. Continued scaling toward 20nm pitch or below will require material system improvements from PS-b-PMMA. Pattern quality for DSA features, such as line edge roughness (LER), line width roughness (LWR), size uniformity, and placement, is key to DSA manufacturability. In this work, we demonstrate finFET devices fabricated with DSA-patterned fins and compare several BCP systems for continued pitch scaling. Organic-organic high chi BCPs at 24nm and 21nm pitches show improved low to mid-frequency LER/LWR after pattern transfer.
Several 27nm-pitch directed self-assembly (DSA) processes targeting fin formation for FinFET device fabrication are studied in a 300mm pilot line environment, including chemoepitaxy for a conventional Fin arrays, graphoepitaxy for a customization approach and a hybrid approach for self-aligned Fin cut. The trade-off between each DSA flow is discussed in terms of placement error, Fin CD/profile uniformity, and restricted design. Challenges in pattern transfer are observed and process optimization are discussed. Finally, silicon Fins with 100nm depth and on-target CD using different DSA options with either lithographic or self-aligned customization approach are demonstrated.
To extend scaling beyond poly(styrene-b-methyl methacrylate) (PS-b-PMMA) for directed self-assembly (DSA), high quality organic high-x block copolymers (HC series) were developed and applied to implementation of sub-10 nm L/S DSA. Lamellae-forming block copolymers (BCPs) of the HC series showed the ability to form vertically oriented polymer domains conveniently with the in-house PS-r-PMMA underlayers (AZEMBLY EXP NLD series) without the use of an additional topcoat. The orientation control was achieved with low bake temperatures (≤200 °C) and short bake times (≤5 min). Also, these process-friendly materials are compatible with existing 193i-based graphoepitaxy and chemoepitaxy DSA schemes. In addition, it is notable that 8.5 nm organic lamellae domains were amenable to pattern development by simple dry etch techniques. These successful demonstrations of high-x L/S DSA on 193i-defined guiding patterns and pattern development can offer a feasible route to access sub-10 nm node patterning technology.
A 27nm-pitch Graphoepitaxy directed self-assembly (DSA) process targeting fin formation for FinFET device fabrication is studied in a 300mm pilot line environment. The re-designed guiding pattern of graphoepitaxy DSA process determines not only the fine DSA structures but also the fin customization in parallel direction. Consequently, the critical issue of placement error is now resolved with the potential of reduction in lithography steps. However, challenges in subsequent pattern transfer are observed due to insufficient etch budget. The cause of the issues and process optimization are illustrated. Finally, silicon fins with 100nm depth in substrate with pre-determined customization is demonstrated.
KEYWORDS: Picosecond phenomena, Polymethylmethacrylate, System on a chip, Scanning electron microscopy, Image segmentation, Photomasks, Etching, Electron beam lithography, Composites, Directed self assembly
Diminishing error tolerance renders the customization of patterns created through directed self-assembly (DSA) extremely challenging at tighter pitch. A self-aligned customization scheme can be achieved using a hybrid prepattern comprising both organic and inorganic regions that serves as a guiding prepattern to direct the self-assembly of the block copolymers as well as a cut mask pattern for the DSA arrays aligned to it. In this paper, chemoepitaxy-based self-aligned customization is demonstrated using two types of organic-inorganic prepatterns. CHEETAH prepattern for “CHemoepitaxy Etch Trim using a self-Aligned Hardmask” of preferential hydrogen silsesquioxane (HSQ, inorganic resist), non-preferential organic underlayer is fabricated using electron beam lithography. Customized trench or hole arrays can be achieved through co-transfer of DSA-formed arrays and CHEETAH prepattern. Herein, we also introduce a tone-reversed version called reverse-CHEETAH (or rCHEETAH) in which customized line segments can be achieved through co-transfer of DSA-formed arrays formed on a prepattern wherein the inorganic HSQ regions are nonpreferential and the organic regions are PMMA preferential. Examples of two-dimensional self-aligned customization including 25nm pitch fin structures and an 8-bar “IBM” illustrate the versatility of this customization scheme using rCHEETAH.
Successful implementation of directed self-assembly in high volume manufacturing is contingent upon the ability to control the new DSA-specific local defects such as “dislocations” or “line-shifts” or “fingerprint-like” defects. Conventional defect inspection tools are either limited in resolution (brightfield optical methods) or in the area / number of defects to investigate / review (SEM). Here we explore in depth a scatterometry-based technique that can bridge the gap between area throughput and detection resolution. First we establish the detection methodology for scatterometry-based defect detection, then we compare to established methodology. Careful experiments using scatterometry imaging confirm the ultimate resolution for defect detection of scatterometry-based techniques as low as <1% defect per area sampled – similar to CD-SEM based detection, while retaining a 2 orders of magnitude higher area sampling rate.
We have performed a systematic study regarding the diblock composition to keep the size of the cylinders relatively constant despite the shape of the guiding pattern. We have also explored how some guiding patterns shapes provide acceptable cylindrical assembly using an EUV exposure system. This study assumes that LER is a random phenomenon which conformably follows the shape of the guiding pattern. While the edges of the guiding pattern have fluctuations related to the LER of the EUV resist, as long as the centroid of the guiding pattern remains constant, the rectification characteristics of DSA permits adequate hole formation. In this paper we include the level of LER a guiding pattern can exhibit given a pre-determined diblock copolymer / homopolymer mixture. As the amount of homopolymer increases, the size and placement of the assembled diblock becomes less sensitive to the guiding pattern’s edge roughness. This study also explores how the addition of homopolymer is only effective up to a point, as a homopolymer-rich blend is not able to assemble properly. One of the concerns about homopolymer-rich mixtures is the effect it has in the formation of defects. Such effect has not been fully characterized but this study serves as the basis for testing optimal combinations of materials and lithography settings for an EUV system, with the end goal to enable contact/via printing at lower EUV source power requirements.
We continue to study the feasibility of using Directed Self Assembly (DSA) in extending optical lithography for High
Volume Manufacturing (HVM). We built test masks based on the mask datatprep flow we proposed in our prior year’s
publication [1]. Experimental data on circuit-relevant fin and via patterns based on 193nm graphoepitaxial DSA are
demonstrated on 300mm wafers. With this computational lithography (CL) flow we further investigate the basic
requirements for full-field capable DSA lithography. The first issue is on DSA-specific defects which can be either
random defects due to material properties or the systematic DSA defects that are mainly induced by the variations of the
guiding patterns (GP) in 3 dimensions. We focus in studying the latter one. The second issue is the availability of fast
DSA models to meet the full-chip capability requirements in different CL component’s need. We further developed
different model formulations that constitute the whole spectrum of models in the DSA CL flow. In addition to the
Molecular Dynamic/Monte Carlo (MD/MC) model and the compact models we discussed before [2], we implement a 2D
phenomenological phase field model by solving the Cahn-Hilliard type of equation that provide a model that is more
predictive than compact model but much faster then the physics-based MC model. However simplifying the model might
lose the accuracy in prediction especially in the z direction so a critical question emerged: Can a 2D model be useful fro
full field? Using 2D and 3D simulations on a few typical constructs we illustrate that a combination of 2D mode with
pre-characterized 3D litho metrics might be able to approximate the prediction of 3D models to satisfy the full chip
runtime requirement. Finally we conclude with the special attentions we have to pay in the implementation of 193nm
based lithography process using DSA.
The first fully integrated SOI device using 42nm-pitch directed self-assembly (DSA) process for fin formation has been demonstrated in a 300mm pilot line environment. Two major issues were observed and resolved in the fin formation process. The cause of the issues and process optimization are discussed. The DSA device shows comparable yield with slight short channel degradation which is a result of a large fin CD when compared to the devices made by baseline process. LER/LWR analysis through the DSA process implied that the 42nm-pitch DSA process may not have reached the thermodynamic equilibrium. Here, we also show preliminary results from using scatterometry to detect DSA defects before removing one of the blocks in BCP.
A study on the optimization of etch transfer processes using 200-mm-scale production type plasma etch tools for circuit relevant patterning in the sub-30-nm pitch regime using directed self-assembly (DSA) line–space patterning is presented. This work focuses on etch stack selection and process tuning, such as plasma power, chuck temperature, and end point strategy, to improve critical dimension control, pattern fidelity, and process window. Results from DSA patterning of gate structures featuring a high-k dielectric, a metal nitride and poly Si gate electrode, and a SiN capping layer are also presented. These results further establish the viability of DSA pattern generation as a potential method for Complementary metal–oxide–semiconductor (CMOS) integrated circuit patterning beyond the 10-nm node.
EUV insertion timing for High Volume Manufacturing is still an uncertainty due to source power and EUV mask infrastructure limitations. Directed Self Assembly (DSA) processes offer the promise of providing alternative ways to extend optical lithography cost-effectively for use in the 10nm node and beyond. The goal of this paper is to look into the technical prospect of DSA technology, particularly in the computational and DFM area. We have developed a prototype computational patterning toolset in-house to enable an early Design –Technology Co-Optimization to study the feasibility of using DSA in patterning semiconductor devices and circuits. From this toolset we can identify the set of DSA specific design restrictions specific to a DSA process and plan to develop a novel full chip capable computational patterning solution with DSA. We discuss the DSA Computational Lithography (CL) infrastructure using the via and fin layers as examples. Early wafer data is collected from the DSA testmask that was built using these new toolsets. Finally we discuss the DSA ecosystem requirements for enabling DSA lithography and propose how EDA vendors can play a role in making DSA Lithography (DSAL) a full-chip viable technology for multiple process layers.
The patterning capability of the directed self-assembly (DSA) of a 42nm-pitch block copolymer on
an 84nm-pitch guiding pattern was investigated in a 300mm pilot line environment. The chemoepitaxy
guiding pattern was created by the IBM Almaden approach using brush materials in
combination with an optional chemical slimming of the resist lines. Critical dimension (CD)
uniformity, line-edge/line-width roughness (LER/LWR), and lithographic process window (PW) of
the DSA process were characterized. CD rectification and LWR reduction were observed. The
chemical slimming process was found to be effective in reducing pattern collapse, hence, slightly
improving the DSA PW under over-dose conditions. However, the overall PW was found to be
smaller than without using the slimming, due to a new failure mode at under-dose region.
Extensive pattern customization will be necessary to realize viable circuit patterns from line-space arrays generated by
block copolymer directed self assembly (DSA). In pattern customization with regard to chemical epitaxy of lamellar
block copolymers, quantitative and precise knowledge of DSA-feature registration to the chemical prepattern is critical.
Here we measure DSA pattern placement error for spatial frequency tripling and quadrupling indexed to specific lines in
the chemical prepattern. A range of prepattern line widths where minimal DSA placement error can be expected is
identified, and a positive correlation between DSA placement accuracy and prepattern uniformity is shown. Considering
the experimental non-idealities present in the chemical prepatterns used in this work that arise from using electron-beam
lithography, we anticipate that 3σ DSA placement errors will be at a minimal level if highly uniform chemical
prepatterns produced by optical lithography are used.
A photomask design flow for generating guiding patterns used in graphoepitaxial DSA processes is proposed and tested. In this flow, a new fast DSA model is employed for DSA structure verification. The execution speed and accuracy of the fast model were benchmarked with our previously reported Monte Carlo method. We demonstrated the process window verification using the OPC/DSA flow with the fast DSA model and compared this with experimental results in the guiding patterns simulated by e-beam lithography.
We employ an alternate approach to Stranski-Krastanow (SK) QD formation involving the use of nanopatterning with
diblock copolymers combined with selective MOCVD growth, enabling QD formation over large surface areas intended
for device application. This approach allows for increased control over the QD size and distribution and elimination of
the problematic wetting layer associated with SK QDs. Cross-sectional TEM studies of the nanopatterned QD active
regions confirm the absence of a wetting layer, and AFM/SEM measurements indicate high QD densities are achieved
(>6x1010 cm-2). Furthermore, the process is applicable to large surface coverage, showing promise for implementation
into long wavelength (λ = 1.3-1.5μm) sources employing either lattice-matched or strained QDs. Preliminary device
results demonstrate LT (up to 170K) InP-based laser operation from devices employing patterned lattice-matched InxGa1-
xAs QD (~ 20 nm dia.) active regions. The formation of high density compressively strained InAs QDs on InP substrates
is also demonstrated using the nanopatterning and selective growth process.
High performance HgCdTe IR detector fabrication on silicon substrates first requires low defect density CdTe buffer
layers to be grown on silicon. The objective of this paper is to demonstrate dislocation reduction in CdTe epitaxial layers
grown on silicon substrate by using intermediate nanocrystalline CdTe buffer layers. Colloidal synthesis of high quality
CdTe nanocrystals was accomplished and spin coating of these CdTe nanocrystals as buffer layers on silicon substrates
was carried out. CdTe layers were grown on these buffered substrates by metalorganic chemical vapor deposition
(MOCVD). However, the incomplete removal of SiO2 on silicon substrate (by chemical treatment) prevented the exact
orientation of the nanocrystals with the silicon substrate and over layer growth of continuous single crystal CdTe
epitaxial film. Two new approaches were further investigated: (i) First a thin film of Ge was grown on Si, followed by
the deposition of thin SiO2 followed by nanopatterning using block co-polymer (BCP) lithography. Transmission
electron microscopy (TEM) showed defect reduction in the CdTe layers grown on these substrates, but the x-ray rocking
curves over a larger area gave wider full width half maximum values compared to that of layers grown on blanket
surfaces. This was attributed to non uniform nanopatterning in these initial studies; (ii) SiO2 coated silicon substrates
were nanopatterned using interference lithography with a honeycomb array of holes. These substrates will be used for
the selective growth of germanium and CdTe by MOCVD.
As an alternate Quantum Dot (QD) fabrication method to self-assembled SK mode QDs, diblock copolymer nano-patterned QDs were investigated. By employing selective growth of QDs on diblock copolymer nano-patterned masks, independence from the problematic wetting layer and controllability on QD size and distribution associated with SK growth mode QDs were realized. The diblock copolymer nano-patterned masks were fabricated using a diblock copolymer template and a dielectric mask, and InxGa1-xAs QDs were selectively grown on patterned GaAs and InP substrates by Metalorganic Chemical Vapor Deposition (MOCVD). The optical properties from diblock copolymer patterned QDs on III-V substrates were investigated at low temperature.
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