As the scaling down of design rule for high-density memory device, the small depth of focus (DoF) budget may be deteriorated by focus leveling errors, which arises in unpredicted reflectivity from multilayer structures on the topographic wafer. The leveling sensors of ASML scanner use near infrared (NIR) range wavelength which can penetrate through most of films using in semiconductor fabrication such as photo-resist, bottom anti reflective coating (BARC) and dielectric materials. Consequently, the reflected light from underlying substructures would disturb leveling sensors from accurate leveling. The different pattern densities and layout characteristics between array and periphery of a memory chip are expected to result in different leveling signals. Furthermore, the process dependent variations between wafer central and edge areas are also considered to yield different leveling performances during wafer exposure.
In this study, lower blind contact immunity was observed for peripheral contacts comparing to the array contacts especially around wafer edge region. In order to overcome this problem, a series of investigations have been carried out. The wafer edge leveling optimization through circuit dependent focus edge clearance (CDFEC) option doesn’t get improvement. Air gauge improved process leveling (AGILE) function of ASML immersion scanner doesn’t show improved result either. The ILD uniformity improvement and step height treatments around wafer edge such as edge exclusion of film deposition and bevel etching are also ineffective to mitigate the blind contact problem of peripheral patterns. Altering the etch hard-mask stack is finally found to be an effective approach to alleviate the issue. For instance, through either containing high temperature deposition advanced patterning film (APF) in the hard-mask or inserting higher opaque film such as amorphous Si in between the hard-mask stack.
In this study, DP (Double Patterning) and DPS (Double Patterning with Spacer) were comprehensively compared through word line layout of 50nm node product, and special focus was put on the assessments of layout discontinuity zones through experimental validation. In conventional flash manufacturing, the lithographic proximity effect and etch loading effect around the array-gap zones have been inherent characteristics to be addressed. For DP process, apart from the overlay error induced pattern displacement and CD non-uniformity, the cross-coupling effects between adjacent features around the array-gap zones by two photo and two etch steps have further complicated the process optimization, therefore careful exploration was carried out to indicate the challenges on process optimization. The DPS can maintain good resultant CD uniformity of dense array through precisely programmed exposure CD and spacer thickness, it may also keep away from the proximity around array-gap zones. But, the second exposure is necessary for trimming the unwanted patterns and delineating the peripheral patterns. In purpose of trimming the unwanted patterns at array-gap zone in the 2nd exposure, the overlay registration will account for the CD control of boundary lines as well as the defectivity around this area.