Dr. Chih-Hung Max Hsieh Profile

Dr. Chih-Hung Max Hsieh

at ASML

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Publications (4)

Proceedings Article | 10 April 2024 Poster + Paper

Evaluation of high NA thin resist metrology and stochastic performance

Tsung-Ta (Alex) Wu, Jill Freeman, Abdalmohsen Elmalk, Li Yun Chang, Tsung Hsien Liu, Yi-Hsin Chang, Max Hsieh

Proceedings Volume 12955, 129552V (2024) https://doi.org/10.1117/12.3010501

KEYWORDS: Metrology, Stochastic processes, Modeling, Critical dimension metrology, Extreme ultraviolet lithography, Semiconducting wafers, Scanning electron microscopy, Data modeling, Matrices, Lithography

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The next milestone in the resolution of high-volume manufacturing will be achieved by High-NA EUV Lithography (HiNA EUVL) systems. In addition to the development of high-NA EUV scanners, the implementation of next generation resist materials remains a critical challenge. Thinner resists are required to accommodate DoF decrease on higher NA physics, which may lead to e-beam metrology and e-beam inspection sensitivity loss due to less electron signal and more severe stochastic failures and variabilities. Due to worse resist imaging contrast and larger pattern roughness in HiNA EUVL, accurate and high resolution CD and defect metrology as well as precise process window (PW) evaluation which considers stochastic failure rate (FR) are needed for resist screening to support the gradual reduction of resist thickness. In this paper we present a thin resist evaluation flow based on next generation e-beam metrology tool (eP6), including metrology setup and qualification and stochastic-aware process window (SAPW) analysis. We will show ADI (after development imaging) evaluation results for a contact hole array with pitch of 32nm for three CAR resist deposited thicknesses from 60nm to 30nm (note: ~40% resist thickness loss post-development). First, we will illustrate some of the metrology responses associated with thin resist and highlight the benefits of improved precision (0.7x), resolution (1.5nm) and sensitivity of next generation metrology tool. For each resist thickness, we will show CD, LCDU and defect measurements across a focus-exposure matrix. LCDU decomposition will be used to quantify SEM, mask, and stochastic contributions to the total measured LCDU. Finally, we will exhibit the SAPW result (Dose-to-Size, Depth of Focus, Exposure Latitude … etc) for the range of resist thicknesses, which can be used to optimize process centering and qualify thin resist performance for HiNA with high correlation coefficient (> 0.9) between measured FR and modeled FR.

Proceedings Article | 27 April 2023 Poster + Paper

Large field of view metrology: detecting critical edge placement error signatures not seen with small field of view in an HVM environment

Mohamed Ridane, Ivy Chen, Jaden Song, Peter Nikolsky, Kuan-Ming Chen, Shinyeong Lee, Sean Park, Kolos Lin, Yu-Chi Su, Kyoyeon Cho, Ethan Yu, James Park, Abdalmohsen Elmalk, Chih-Hung Hsieh, Alexander Serebryakov, Lei Zhang, Taekwon Jee, Joonsang You, Hong-Goo Lee, Jongmin Park, Jungchan Kim, Sang-Woo Kim, Seungmo Hong, Jaewook Seo

Proceedings Volume 12496, 124963C (2023) https://doi.org/10.1117/12.2659692

KEYWORDS: Metrology, Semiconducting wafers, High volume manufacturing, Line width roughness, Critical dimension metrology, Scanning electron microscopy, Optical lithography, Environmental sensing, Edge detection, Overlay metrology

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Proceedings Article | 26 May 2022 Presentation + Paper

Absolute overlay measurement based on voltage contrast defect inspection with programmed misalignments for DRAM devices

Moosong Lee, Jinsun Kim, Dohyeon Park, Yeeun Han, Junseong Yoon, Seung Yoon Lee, Chan Hwang, Achim Woessner, Cyrus Tabery, Miao Wang, Antonio Corradi, Young-Hoon Song, Yun-A Sung, Thomas Kim, Aileen Soco, Jason Kim, Chih-Hung Hsieh

Proceedings Volume 12053, 1205315 (2022) https://doi.org/10.1117/12.2626721

KEYWORDS: Overlay metrology, Semiconducting wafers, Defect inspection, Metrology, Inspection, Standards development, Image processing, Electronics, Etching, Electrons

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Proceedings Article | 22 February 2021 Presentation + Paper

Edge placement error wafer mapping and investigation for improvement in advanced DRAM node

Kuan-Ming Chen, Wolfgang Henke, Ji-Hoon Jung, Ewa Kasperkiewicz, Anita Bouma, Rizvi Rahman, Gratiela Isai, Gwang-Gon Kim, Sotirios Tsiachris, Jae-Doug Yoo, Yuna Park, JaeYoung Park, Jonggeun Won, Nang-Lyeom Oh, Hsin-Yu Chen, WeiTai Lin, Chih-Hung Hsieh, Kuo-Feng Pao, Kyoyeon Cho, Abdalmohsen Elmalk, Sudharshanan Raghunathan, Taekwon Jee, Seung-Uk Jeong, Jeongwoo Jae, Sang-Woo Kim, Dongyoung Lee, Jungchan Kim, WonKwang Ma, Sang-Ho Lee, Chan-Ha Park

Proceedings Volume 11611, 116111V (2021) https://doi.org/10.1117/12.2584149

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Overlay metrology, Optical lithography, Metrology, Visualization, Statistical analysis, Lithography, Graphic design, Etching

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