3D-NAND manufacturers are racing to increase the storage capacity by increasing the number of stacked layers. As the increase of the number of stacked layers, complex process, films stress and deep-etch tilting effects were observed to affect the device overlay control significantly. Traditional optical overlay metrology via scribe-lane image based overlay (IBO) has its constraint to entirely reflecting in-device overlay behavior because of the differences on pattern density, film stack and stress to memory array. In this study, Patterned Wafer Geometry (PWG) tool was adopted to collect wafer shape step-by-step. The in-plane deviation (IPD) and Gen4 overlay derived from wafer shape was used as efficient indexes to distinguish which metrology is representative of indevice overlay for critical layers. High voltage scanning electron microscope (HV-SEM) and optical scatterometry critical dimension measurement (SCD) were adopted separately combining with traditional scribe-lane IBO metrology for in-device overlay improvement through applying non-zero offset (NZO) overlay compensation at different photo layers.
KEYWORDS: Overlay metrology, Single crystal X-ray diffraction, Metrology, Semiconducting wafers, 3D metrology, Control systems, Process modeling, Polishing, Etching, Image processing
As device dimensions continuously shrink in semiconductor manufacturing, even tighter overlay control is indispensable to secure good device yield. Using traditional optical overlay metrology via scribe-lane marks it is challenging to achieve good intra-field high-order process correction (iHOPC) due to the limited mark count and uneven mark distribution. Also the scribe-lane based metrology may not fully represent the in-device behavior in some cases. In order to achieve improved accuracy and precision of in-device overlay control, new metrology methodology solution is required. In this paper, three complementary overlay metrology techniques – high voltage scanning electron microscope (HV-SEM), optical scatterometry critical dimension measurement (SCD), and traditional scribe-lane based optical overlay metrology – were adopted for in-device overlay improvement. In 3D NAND device production, in-device overlay measurement is getting more challenging due to the thicker or complex film stack. Though both HV-SEM and SCD are able to measure in-device patterns via capturing buried structures, their different tool principles make them suitable in different situations. Through applying non-zero offset (NZO) overlay compensation at photo exposure, the in-device overlay performance can be enhanced by iHOPC, which is enabled by incorporating high-density in-device sampling measurements from HV-SEM and SCD into traditional optical scribe-lane optical overlay measurements. The improved overlay performance was demonstrated for different process layers in this study.
Optical overlay metrology has been adopted for years as baseline for overlay control in semiconductor manufacturing. More stringent overlay budget for securing good product yield has been required as device dimension shrinkage. For effective and tight overlay control, the traditional optical overlay metrology has faced two primary challenges of increasing the measurement accuracy and minimizing the measurement variance between overlay mark in scribe lane and in-die device pattern. Overlay mark asymmetry is one of the general factors to induce optical overlay metrology error. While 3D-NAND deep-etch processes would induce within-wafer mark asymmetry which worsens measurement robustness of optical overlay metrology. Accurately determining on-product overlay (OPO) errors at both after-develop inspection (ADI) and after-etch inspection (AEI) is also desirable in 3D-NAND process for applying non-zero offset (NZO) at photo exposure. To address the measurement robustness of optical overlay metrology in 3D-NAND process, also for accurately bridging the scribe lane based optical overlay metrology to OPO metrology, a complementary overlay metrology by high voltage scanning electron microscope (HV-SEM) was adopted as the reference metrology for optimizing the optical measurement condition on scribe lane targets. In this paper, the measurement accuracy of imaging-based overlay (IBO) target under various optical conditions was calibrated by HV-SEM. HV-SEM can measure both the scribe-lane and in-device targets via capturing buried structures, and it was employed to bridge the measurement results from IBO and in-device target. Then the optimal optical metrology can be decided for both ADI and AEI to facilitate effective advance process control (APC) and NZO purpose.
In order to meet the increasing storage capacity demand and reduce bit cost of NAND flash memories, 3D stacked vertical flash cell array has been proposed. In constructing 3D NAND flash memories, the bit number per unit area is increased as increasing the number of stacked layers. However, the increased number of stacked layers has made the film stress control extremely important for maintaining good process quality. The residual film stress alters the wafer shape accordingly several process impacts have been readily observed across wafer, such as film deposition non-uniformity, etch rate non-uniformity, wafer chucking error on scanner, materials coating/baking defects, overlay degradation and critical dimension (CD) non-uniformity.
The residual tensile and compressive stresses on wafers will result in concave and convex wafer shapes, respectively. This study investigates within-wafer CD uniformity (CDU) associated with wafer shape change induced by the 3D NAND flash memory processes. Within-wafer CDU was correlated with several critical parameters including different wafer bow heights of concave and convex wafer shapes, photo resists with different post exposure baking (PEB) temperature sensitivities, and DoseMapper compensation. The results indicated the trend of within-wafer CDU maintains flat for convex wafer shapes with bow height up to +230um and concave wafer shapes with bow height ranging from 0 ~ -70um, while the within-wafer CDU trends up from -70um to -246um wafer bow heights. To minimize the within-wafer CD distribution induced by wafer warpage, carefully tailoring the film stack and thermal budget in the process flow for maintaining the wafer shape at CDU friendly range is indispensable and using photo-resist materials with lower PEB temperature sensitivity is also suggested. In addition, DoseMapper compensation is also an alternative to greatly suppress the within-wafer CD non-uniformity but the photo-resist profile variation induced by across-wafer PEB temperature non-uniformity attributed to wafer warpage is uncorrectable, and the photo-resist profile variation is believed to affect across-wafer etch bias uniformity to some degree.
Layout pattern density impacts mask critical dimension uniformity (MCDU) as well as wafer critical dimension
uniformity (WCDU) performances in some aspects. In patterning the dense contact array with negative tone
development (NTD) process, the abrupt pattern density change around the array edge of a NTD clear tone reticle arises
as a very challenging issue for achieving satisfactory WCDU. Around the array boundary, apart from the MCDU greatly
impacted by the abrupt pattern density change, WCDU in lithographic process is also significantly influenced by the
optical flare and chemical flare effects.
This study investigates the pattern density effect induced MCDU and WCDU variations. Various pattern densities are
generated by the combination of fixed array pattern and various sub-resolution assist feature (SRAF) extension regions
for quantifying the separated WCD variation budget contributed by MCD variation, chemical flare effect and optical
flare effect. With the proper pattern density modulation outside the array pattern on a clear tone reticle, MCD variation
across array can be eliminated, optical flare and chemical flare effects induced WCD variation is also greatly suppressed.
Contact-hole patterning is even more challenging than line/space patterning because of the lower image contrast and smaller process window. To enable single exposure solution of 40-45nm half pitch contact-hole at this nearly resolvable limit of current 1.35NA ArF immersion lithography, negative tone development (NTD) process, source mask co-optimization (SMO) methodology and free-form source were explored in this study. The optimization of free form source and mask for NTD process was firstly carried out via Brion Tachyon SMOTM software. The wafer-level performance was then compared for different mask layout solutions and different mask types. A manufacture worthy process window was achieved for 40nm technology node Flash memory product through the combination of free-from source, SMO and NTD technologies. In the performance comparison for mask types, 6% HTPSM performed wider DoF and exposure latitude for all three pitch designs. But OMOG mask is superior to 6% HTPSM on mask and wafer CD uniformity. To further improve the overlapping process window, preserving the SMO layout solution as possible for the sparse environments and minimizing the SRAF writing errors were proposed as the two most critical tuning knobs.
A post-developed defect unlike the traditional satellite spot was found in the self-aligned double patterning (SADP)
process flow. The defects tend to happen around boundary adjacent to the clear pattern area and finally yield pattern
distortion or bridging (called "distortion" hereafter). This distortion defect has been characterized as yield killer since it
causes word-line bridging after etching. This paper will describe the effect of resist type, top anti-reflective coating
(TARC), various development puddle/rinse schemes, hard bake (HB) and advanced defect reduction (ADR) function on
the distortion defect performance. TARC has been indentified as an effective solution to reduce the conventional satellite
defect but the experimental result on eliminating the distortion defect is not obvious. In resist processing, post-developed
HB temperature showed strong correlation to the distortion defect count. The distortion defect reduces as lowering the
HB temperature, and furthermore the defect can be fully eliminated by experimentally skipping the HB step. The
combination of multiple cycles of wafer agitation in the development puddle, double development puddle and scanning
rinse significantly suppresses the defect count. However, the aggressive development recipe has made the process time
too long to be acceptable for mass production. To minimize the throughput loss, ADR is another solution to eliminate the
distortion defect.
In patterning the via-hole, uneven hole-size and missing-hole defects were identified through after etch inspection (AEI),
and these defects were characterized as yield killer since it led to electrical open. Through the after development
inspection (ADI) and AEI comparison, the uneven hole-size and missing-hole defects are attributed to the postdeveloped
satellite spots. The distribution of satellite spots always show a strong photo field map that is discovered to
correlate with the local pattern density in mask scribe lane. Apart from the possible modifications on pattern density in
the scribe lane by retooling the photo mask, this paper describes the work done in reducing the satellite defect. Several
development experiments including multiple wafer agitation cycles of dynamic puddle, multiple cycles of scanning rinse,
pre-wet before development, wafer rotation speed in rinse, wafer rotation speed in drying and advanced defect reduction
(ADR) function of track were carried out. The multiple cycles of scanning rinse coupling with the optimal wafer rotation
speed of rinse effectively suppresses the count of satellite spots. Pre spin dry in advance of the deionized water (DIW)
rinse to minimize the pH shock is also effective to reduce the defect count. Multiple cycles of development puddle and
scanning rinse have a synergy effect to lower defectivity up to complete suppression of satellite defect. To minimize the
throughput loss induced by the long development time, ADR is proposed as better candidate for fully eliminating the
satellite defect.
DPS (Double Patterning with Spacer) has been one of the most promising solutions in flash memory device
manufacturing. Apart from the process complexity inherent with the DPS process, the DPS process also requires more
engineering efforts on alignment technique compared to the single patterning. Since the traditional alignment marks
defined by the core mask has been altered hence the alignment mark recognition could be challenging for the subsequent
process layers.
This study characterizes the process influence on the traditional ASML VSPM (Versatile Scribelane Primary Marks)
alignment mark, and various types of sub-segmentations within VSPM marks were carried out to enable the alignment
and find out the best performing alignment marks. The design of the transverse and vertical sub-segmentations within the
VSPM marks is aimed to enhance the alignment signal strength and mark detectability. Alignment indicators of WQ
(Wafer Quality), MCC (Multiple Correlation Coefficient) and ROPI (Residual Overlay Performance Indicator) were
used to judge the alignment performance and stability. A good correlation was established between sub-segmentations
and wafer alignment signal strength.
In this study, DP (Double Patterning) and DPS (Double Patterning with Spacer) were comprehensively compared through word line layout of 50nm node product, and special focus was put on the assessments of layout discontinuity zones through experimental validation. In conventional flash manufacturing, the lithographic proximity effect and etch loading effect around the array-gap zones have been inherent characteristics to be addressed. For DP process, apart from the overlay error induced pattern displacement and CD non-uniformity, the cross-coupling effects between adjacent features around the array-gap zones by two photo and two etch steps have further complicated the process optimization, therefore careful exploration was carried out to indicate the challenges on process optimization. The DPS can maintain good resultant CD uniformity of dense array through precisely programmed exposure CD and spacer thickness, it may also keep away from the proximity around array-gap zones. But, the second exposure is necessary for trimming the unwanted patterns and delineating the peripheral patterns. In purpose of trimming the unwanted patterns at array-gap zone in the 2nd exposure, the overlay registration will account for the CD control of boundary lines as well as the defectivity around this area.
AlCu PVD (Physical Vapor Deposition) induced overlay shift has been a critical concern for non-damascene
metallization process to tackle with the ever decreasing overlay tolerances. In this study, a new approach was
demonstrated to effectively eliminate the AlCu PVD induced overlay shift. With measuring the metal-to-contact
registration before the metal deposition and feeding forward the values for metal-to-contact overlay compensation at the
metal photo process, the metal-induced shift can be optimally managed. Besides, an investigation was also carried out to
figure out the suitable measurement target with least sensitive to process parameter variations at after contact etch, after
contact W CMP and after metal etch. As a consequence, the conventional wide-trench overlay target has been identified
to be the more susceptible to the process variation and easily results in measurement reading error. Compared to the
conventional wide-trench target, a 0.2um width narrow trench target performed the better mark integrity for our feed-forward
compensation approach. Finally, the feed-forward compensation in combination with narrow width overlay
mark has demonstrated its effectiveness on managing the AlCu-PVD induced overlay shift.
As the semiconductor feature size continues to shrink, the high NA lithography has become a reality. Coupling with high NA lithography, both the critical dimension control and the insufficient resist thickness for etch mask are becoming major challenges for lithographers. Hence two things are highly desired, one is an effective anti-reflective coating (ARC) strategy to maintain low reflectance for good critical dimension (CD) uniformity (CDU) control, and the other is combined ARC and hard-mask concept to satisfy both lithography and etch performance needs for feature patterning. In this study, a dual dielectric anti-reflective coating (dual-DARC) was first demonstrated as an effective ARC for contact application with high NA lithography. The ordinary single DARC is very sensitive to the thickness variation of underlying films, resulting in a >45nm contact CD variation at interlayer dielectric (ILD) thickness variation of ±150nm induced by CMP process. Unlike the single DARC, the dual-DARC performs a less CD variation of ~5nm at the same film thickness variation. By extending the dual-DARC concept to combined ARC/hard-mask application to contact and poly patterning, several ARC/hard-mask schemes were compared by reflectance control, CD uniformity control and etch hard-mask performance. Apart from the good reflectance and CD uniformity control of dual-DARC-like schemes, the most attractive is that the proper use of dual-DARC concept to hard-mask application, the tight thickness control is not necessary for the bottom layer and you can just tailor the bottom layer's thickness to meet the individual process needs.
Resolution and through-pitch common process window are two key factors to tackle for successful small contact process manufacturing. The off-axis illumination (OAI) in combination with assist feature and attenuated phase-shift mask (APSM) is the most common used solution. However, it is still difficult to avoid problematic pitches and get a sufficient through-pitch common process window for practical use unless forbidding the problematic pitches by design rule. A novel perpendicular assist feature (PAF) is proposed in this investigation, it is composed of a set of sub-resolution space perpendicular to the contact hole edge. The optical principles, design guidelines and tuning flow of PAF were described in this paper. The performance comparison between conventional assist feature (CAF) and PAF was also conducted in this study. Consequently, the PAF demonstrated better through-pitch photo performances on CD uniformity and mask error enhancement factor (MEEF), and most importantly, the problematic pitches issue occurred at CAF configuration was successfully eliminated.
The radioactive tracer technique was applied to investigate the diffusion and adsorption behaviors of metallic impurities (i.e., Ba, Cs, Zn and Mn) from chemically amplified photoresist onto silicon-based underlying substrates. Two important process parameters, i.e., baking temperatures and substrate types (e.g., bare silicon, polysilicon, silicon dioxide, and silicon nitride) were evaluated. Our results indicated that the transition metals (Zn and Mn) could have lower diffusion ratios than alkali metal (Cs) and alkaline earth metal (Ba), irrespective of the substrate types and baking temperatures. It was found that the transition metals would form stable complex with the coexisting solvents and/or hydrolysis species in the photoresist layer. The size of metal complex, the drag force of solvent evaporation, and the baking process were found to have significant effects on impurity migration. In addition, a new diffusion-adsorption model was proposed to explain the effect of substrate types. Our model successfully explained the substrate effect for bare silicon with lower diffusion ratios as compared with silicon nitride. The coverage of substrate surface with silanol group could be attributed to the formation of native oxide. The effects, including the concentration of surface adsorption metal, the equilibrium constant, the surface concentration of silanol group, the concentration of metallic impurity and the pH value, played very important role on the diffusion ratios for Ba, Cs, Zn and Mn.
The novel radioactive tracer technique was applied to investigate the migration of cesium, manganese and zinc impurities from deep ultraviolet photoresist into underlying substrate. Two important process parameters, viz., baking temperatures and substrate types (i.e., bare silicon, polysilicon, silicon oxide and silicon nitride), were evaluated. Our results indicated that the migration ratios were all below 6%, irrespective of baking temperatures and substrate types. The substrate types did not appear to strongly affect the metallic impurity out-diffusion from deep ultraviolet photoresist. However, solvent and/or water evaporation due to temperature change was found to have a significant effect on metal migration. The net driving force of impurity changes with temperature and the impurity diffusion can be classified into four types. Based on the proposed types, the obtained migration ratios can be realized. A new model, together with a new parameter, was proposed to describe the out-diffusion behavior of impurities from deep ultraviolet photoresist. The diffusion profile of photoresist was depicted based on diffusion equations and the migration ratios. This model could explain the migration ratios of metallic impurities in photoresist layers under various baking conditions.
The modification of the i-line resist structure after spiking with various amount of poly(4-vinylphenol) polymer is characterized by the spectra of UV visible and gel permeation chromatography. The chemical structure of photoactive compound is found to be unchanged after modification, while slight change in the polymer chain is observed. The resist layer coated onto the wafer is characterized by various methods including n and k analyzer, Nanospec, Fourier transform IR red, thermogravimetric analysis, and differential scanning calorimetry to fully evaluate the film properties in terms of porosity, thickness, vibrational spectrum, and thermal stability. Our thermal analysis results show that the resists are mainly decomposed in three stages. The photoactive compound is found to decompose during the first stage, while the polymer decomposes during the latter stages. The resist exposure parameters, namely, A, B and C at 365 nm are determined by the absorbance measurement. The extracted parameters are further used in the resist profile simulation by PROLITH/2. It is shown that the spiking of poly(4-vinylphenol) polymer into the resist can improve the resolution and linearity for dense lines. In addition, the swing effects can be reduced by up to 35 and 31 percent for dense and isolated lines after resist modification, respectively.
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