Imec has developed a new technology to integrate and interconnect back-contact solar cells into modules, based on
embedding cells in silicone on top of a glass substrate. This technology aims at an improved optical performance and
reliability (through the use of silicones and low-temperature metallization). One of the additional advantages is that the
technology is suitable for integrating very thin cells into modules: whereas standalone interconnection of such fragile
thin cells, e.g. tabbing and stringing, would significantly lower the throughput yield due to breakage, the cells are better
protected if they are embedded inside silicone.
The paper will first elaborate on the process flow, the background and motivation, advantages, drawbacks and
limitations, and technical aspects of the developed technology. Then it will present the results of the measurements on
the performance of functional solar cells processed into modules using this technology, discussing losses and loss
mechanisms. Then, the approach towards determining the reliability of the module will be presented, indicating how
imec aims at building up an ageing model, and elaborating the results on the failure mode and effect analysis, modeling,
characterization and reliability testing.
Zero-level packaging, i.e. the encapsulation of the MEMS device at wafer level, is an essential technique for MEMS miniaturization and cost reduction. A large number of different capping and sealing materials and techniques can be used. However, the testing and qualification of this type of packaging of MEMS devices requires special techniques. A number of conventional and new characterization techniques for mechanical and hermeticity testing are presented, as well as an overview about outgasing measurements and reliability testing.
The effect of the deposition parameters and Ge content on the stress gradient in poly-SiGe films was investigated. The films, ranging in thickness from 1.2 to 2.3 μm, were deposited by chemical vapor deposition (CVD) at 450 °C and plasma enhanced chemical vapor deposition (PECVD) at 520 °C. The Ge content was varied between 45 and 64 at%. Xray diffraction revealed that both PECVD and CVD films were polycrystalline. The stress gradient was determined by
measuring the deflection of 1 mm long released cantilevers. The stress gradient was found to decrease with increasing Ge content. A CVD film with 55 at% Ge was thinned using a very low power SF6/O2 plasma. The stress gradient was measured as a function of film thickness. The stress profile was calculated by matching the bending moment of the calculated profile to the bending moment obtained from the measured stress gradient. The largest change in stress occurs right at the thin film/substrate interface. PECVD films were found to possess a lower stress gradient compared to CVD films with similar thickness. This was explained by differences in TEM microstructure: CVD films have more Vshaped grains, while PECVD films have more columnar grains.
In this work the etching of different Si-oxide, Si-nitride and metal layers in HF:H2O 24.5:75.5, BHF:glycerol 2:1 and vapor HF is studied and compared. The vapor HF etching is done in a commercially available system for wafer cleaning, that was adapted according to custom specifications to enable stiction-free surface micro- machining. The etch rates as a function of etching method, time and temperature are determined. Moreover, the influence of internal and external parameters on the HF vapor etching process are analyzed before choosing the standard HF vapor etch technique used for comparing the etching behavior of the different films.
This paper reports on the fabrication of innovative counter electrodes for the development of a new Scanning Atom Probe (SAP) instrument. A process using thick spin-on dielectrics, deep reactive ion etching and photolithography has been developed for the realization of the counter electrodes. The novel structure is a two-terminal device in the form of a hollow cone shape, with tow electrodes separated by a dielectric layer. Different counter electrode design versions are presented, with the focus on the results for the first iteration. Electrical testing of the insulating layer is performed to investigate the material suitability for the operating conditions of the SAP instrument. Details regarding the design and fabrication procedure for the different designs, with emphasis on the process flow for the non standard steps, are also presented.
In this work, die-to-die CD-variations across a wafer are investigated as a potential important contribution to the global gate CD-control. Measuring the non-uniformity in different experiments using CD-SEM and ELM revealed different parameters, impacting the measured non-uniformity value. It will be pointed out that the measurement itself can have a significant contribution to the measured 3(sigma) -value, especially using CD-SEM, if the level in non-uniformity is low. Further on, it will be shown that the choice of resist and developer chemistry can have a high impact on the i-W CD non-uniformity. Moreover, the potential impact of exposure and track processing will be outlined, and an optimization methodology will be presented. Finally, it will be shown that gate process integration, in particular BARC- and POLY-etching, is increasing the i-W CD non-uniformity. This is affecting the ELM-results, despite the high precision and repeatability of these measurements. This ELM-variation, as well as the overall i-W CD non- uniformity should be taken into account when using ELM or CD-SEM as a metrology tool for process window characterization.
We report on a micromachined silicon chip that is capable of providing a high-throughput functional assay based on calorimetry. A prototype twin microcalorimeter based on the Seebeck effect has been fabricated by IC technology and micromachined postprocessing techniques. A biocompatible liquid rubber membrane supports two identical 0.5 X 2 cm2 measurement chambers, situated at the cold and hot junction of a 666-junction aluminum/p+-polysilicon thermopile. The chambers can house up to 106 eukaryotic cells cultured to confluence. The advantage of the device over microcalorimeters on the market, is the integration of the measurement channels on chip, rendering microvolume reaction vessels, ranging from 10 to 600 (mu) l, in the closest possible contact with the thermopile sensor (no springs are needed). Power and temperature sensitivity of the sensor are 23 V/W and 130 mV/K, respectively. The small thermal inertia of the microchannels results in the short response time of 70 s, when filled with 50 (mu) l of water. Biological experiments were done with cultured kidney cells of Xenopus laevis (A6). The thermal equilibration time of the device is 45 min. Stimulation of transport mechanisms by reducing bath osmolality by 50% increased metabolism by 20%. Our results show that it is feasible to apply this large-area, small- volume whole-cell biosensor for drug discovery, where the binding assays that are commonly used to provide high- throughput need to be complemented with a functional assay. Solutions are brought onto the sensor by a simple pipette, making the use of an industrial microtiterplate dispenser feasible on a nx96-array of the microcalorimeter biosensor. Such an array of biosensors has been designed based on a new set of requirements as set forth by people in the field as this project moved on. The results obtained from the prototype large-area sensor were used to obtain an accurate model of the calorimeter, checked for by the simulation software ANSYS. At present, the sensor chip has been designed. Future publication(s) will deal with this part of the work.
Transmissive single crystal AMLCD light valves have recently drawn much attention for application in flat panel displays. The active matrix circuits are fabricated on SIMOX wafers and then transferred to glass. Circuit transfer consists in bonding a CMOS processed SIMOX wafer to a Pyrex glass substrate, thinning the SIMOX wafer and opening the contact pads. The pixel electrodes are made in polysilicon to allow standard CMOS processing. This paper discusses the transparency of the poly electrode and evaluates the potential of anodic bonding and adhesive bonding for circuit transfer. A major challenge for anodic bonding is the protection of the device dielectrics against the high voltages applied during bonding. A test chip was designed to investigate different ways of circumventing breakdown of the dielectrics. A method for adhesive bonding is discussed that assures good uniformity of the thickness of the epoxy layer and avoids the inclusion of air bubbles. It is demonstrated that the epoxies are resistant to the chemicals used for thinning the silicon substrate.
The electrical contacts are of crucial importance for the ultimate performance of (micro)relays. In this paper, the contact resistance of hard-contact relays is experimentally studied as a function of the contact force, the apparent contact area and the cleanliness of the contact surfaces. A simple test bench set-up is used to measure the contact resistance in air as a function of the contact force and the contact area. Forces range from 50 mgf to several gf. The contacts have a round shape with diameters ranging from 100 micrometers to 500 micrometers . The resistance decreases with increasing force and increasing area. Above force of approximately 2 gf, the contact resistance becomes fairly stable, i.e., independent of the applied force. The contact resistance stabilizes at values varying from 30 to 50 m(Omega) depending on the area. The measured contact resistance values for a 50 mgf contact force scatters between 50 m(Omega) and 0.7 m(Omega) due to the presence of a contaminating film on the contact surfaces. The scatter in measured values reduces to less than 10 m(Omega) when the contact force is around 4 gf, which again emphasizes that a certain minimum force is required for a reliable contact.
We have fabricated 1.8-in., 86,400-pixel poly-Si thin-film-transistor (TFT) LCDs with a novel TFT structure and a storage-capacitance (Cst) arrangement. The TFTs have a self-aligned offset structure that is made by a simple process without using an additional mask. With this structure, we have reduced the OFF current, and hence attained a high ON/OFF current ratio of 107. A novel Cst line arrangement called "modified on Cst gate" was adopted. Gate lines and Cst lines are arranged alternately, and the (n - 1)'th Cst line is connected to the n'th gate line at the line's end. The Cst line works as backup for the gate line. Consequently, we have obtained TFT arrays with no line defects (240 gate lines). By using these techniques, we have succeeded in fabricating a high-performance 1.8-in. poly-Si TFT-LCD panel for a projection TV.
We have fabricated 1.8-inch and 86,400-pixel poly-Si TFT-LCDs with a novel TFT structure and a storage capacitance (Cst) arrangement. The TFTs have a self-aligned offset structure which is made by a simple process without using an additional mask. With this structure, we have reduced the OFF current, and hence, attained a high ON/OFF current ratio of 107. A novel Cst line arrangement called 'modified Cst on gate' was adopted. Gate lines and Cst lines are arranged alternatively, and the (n-1)-th Cst line is connected to the n-th gate line at the line's end. The Cst line works as redundancy of the gate line. Consequently, we have obtained TFT arrays with no line-defects (240 gate lines). By using these techniques, we have succeeded in fabricating a high-performance 1.8-inch poly-Si TFT-LCD panel for a projection TV.