In this contribution we describe a Tachyon based flow to measure mask error systematics and simulate their impact to wafer level, as well as determining the contribution of these errors to OPC model calibration error. The dataset consists of 1000 OPC model calibration patterns for an N5 via layer for which we have a quadruplet of post-OPC GDS, simulated mask contour, mask CDSEM image and wafer CDSEM image as shown in Figure 2. First we examine the error at the mask using a combination of MXP (for metrology) and Tachyon LMC (for contour comparison) software products. Again using LMC we can simulate to wafer level using the simulated mask contour, and the measured mask contour as input. This allows us to correlate mask error to expected wafer error. Finally we calibrate OPC models to the measured wafer data using the various mask representations (postOPC Manhattan, simulated and measured) as input and observe the effect on OPC model error. This is done using Tachyon FEM+ with term based resist models of varying complexity.
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