We compare the noise performance of two optimized readout chains that are based on 4T pixels and featuring the same bandwidth of 265kHz (enough to read 1Megapixel with 50frame/s). Both chains contain a 4T pixel, a column amplifier and a single slope analog-to-digital converter operating a CDS. In one case, the pixel operates in source follower configuration, and in common source configuration in the other case. Based on analytical noise calculation of both readout chains, an optimization methodology is presented. Analytical results are confirmed by transient simulations using 130nm process. A total input referred noise bellow 0.4 electrons RMS is reached for a simulated conversion gain of 160μV/e−. Both optimized readout chains show the same input referred 1/f noise. The common source based readout chain shows better performance for thermal noise and requires smaller silicon area. We discuss the possible drawbacks of the common source configuration and provide the reader with a comparative table between the two readout chains. The table contains several variants (column amplifier gain, in-pixel transistor sizes and type).
This paper revisits the fundamental theory of thermal noise in the MOS transistor. It has been recognized quite early that carrier velocity saturation and eventually also carrier heating degrades the thermal noise performance of short-channel MOS devices. This degradation is evaluated in terms of the delta thermal noise parameter defined initially by van der Ziel as the ratio between the thermal noise conductance at the drain and the channel conductance at VDS=0. For long-channel devices this factor is equal to 2/3. Today, there is still a controversy about what the value of this factor actually is for short-channel devices. Some authors measured a significant degradation of up to 7, attributing it mainly to carrier heating. Some other measured values that where always smaller than 2 on several devices over several technologies and pretend that there is no need of carrier heating to explain this moderate degradation, assuming that velocity saturation only can explain it. More recently, some other authors attribute this degradation to the effect of channel-length modulation. Based on a truly physical charge-based model, this paper tries to clarify the contribution of these different effects on δ. It also highlights the fact that for circuit designers, the real important parameter is not so much the δ factor but rather the ratio of the thermal noise to the transconductance at the same bias point defined as the γ thermal noise excess factor.
This paper presents a non-quasi-static (NQS) thermal noise model of the MOS transistor that is valid in all modes of operation, from weak to strong inversion, and up to frequencies which are near or above the NQS cut-off frequency. It is shown that in addition to the well-known induced gate noise (IGN) there is also an induced substrate noise that is generated and that the source and drain noises are also affected. All prior publications on the subject only deal with IGN in strong inversion regime. It is shown that significant differences are obtained for moderate and weak inversion operation. The paper starts with a brief review of NQS model valid in all modes of operation. It then presents a general thermal noise model using four noisy current sources. The power spectral and cross power spectral densities of these noise sources are computed. A first-order approximation is then derived and compared to the complete model. Noise excess factors for the drain and the gate noise are then calculated and the correlation coefficient between the drain and the gate noise is obtained. It is shown that this correlation factor is always null in conduction (VD = VS), and varies in saturation between j0.6 in weak inversion to j0.4 in strong inversion. To our knowledge, it is the first time that a complete HF thermal noise model of the MOST is presented, that is valid in all modes of inversion and up to and above the NQS cut-off frequency.
SC267: Si-based High Performance Transistor Modeling for the Design of RF and High-speed ICs
This course provides a comprehensive overview of MOS, bipolar and HBT transistor modeling with emphasis for RF and high-speed IC design. Using CMOS for implementing RF circuits for wireless communications has been demonstrated. One of the obstacles for a large industrial use of CMOS in RF circuits is the lack of good MOS transistor models that are valid up to RF. The first module of this course describes the special aspects of the MOS transistor modeling for RFIC design, including noise, NQS, small and large signal modeling. Bipolar transistors have been the workhorses in analog/RF application for decades. Modern SiGe HBT has emerged as choice of technology for low-cost RF systems-on-chip. The second module will identify the bipolar compact modeling status and introduce advanced models such as HICUM, MEXTRAM and VBIC. In particular, physical effects, high-current effects and lateral scalability that are relevant for designing high-speed circuits are discussed with real data. Model parameter extraction, in particular from the real-world characterization is crucial and remains as an important practical issue addressed in the 3rd module of this course.