Mask synthesis and correction flows are becoming increasingly complex in order to deal with increasingly smaller lithography, resist, and etch effects that also increase in importance with increasingly smaller feature sizes. Time-to-mask is also a significant factor in production environments which leads tapeout teams to adopt correction strategies that usually only address effects at the best process condition. As a result, users frequently find hotspots, or process failures, when performing a final lithography verification step using multiple process conditions. In many cases, under production pressure to decrease time-to-mask, tapeout teams choose to correct these hotspots in the fastest manner possible. Performing rule-based fixes to the post-correction layout is usually the fastest method available. This paper will explore using rule-based, post-correction hotspot fixes in a flow using pattern matching. Pattern matching will be used to cluster the post-correction patterns into similar types which will be fixed by different algorithms for each type. Further, pattern matching will be used to find all instances of each pattern to mark for fixing along any similar patterns that may have been missed by the lithography check, or those that received asymmetrical correction.
As the design layout of integrated circuits (ICs) is continually scaling down, sub-resolution assist features (SRAF) have been extensively used in resolution enhancement technique (RET) applications to enhance lithography printing fidelity and widen the manufacturing process window (PW). With conventional SRAF insertion techniques, rule-based SRAF (RB-SRAF) and model-based SRAF (MB-SRAF) methods have been widely adopted. The typical RB-SRAF is an efficient method to generate SRAFs consistently for simple designs, but cannot be optimized for multiple critical patterns or complex layout schemes. Although MB-SRAF is able to achieve better process window as well as reducing conflicts between placement rules and clean-up rules, many iterations for convergence and extremely high computational costs are required. The explosion of machine learning techniques could facilitate the complex processes of mask optimization, such as SRAF insertion. In this paper, generative adversarial network was studied on a Via layer of advanced 3D NAND flash memory, by training target images and Inverse Lithography Technology (ILT) images of target patterns. GAN models, pix2pix and CycleGAN, were first trained and then utilized to synthesize realistic ILT images. These ILT images were eventually translated to polygons of SRAF with simplification process and mask manufacturing rules check (MRC) constraints. The simulation results demonstrate that CycleGAN approach can place SRAF with comparable performance to mask optimization (MO) result which was optimized by the Tachyon Source-Mask Optimizer (SMO). Most importantly, the efficiency of SRAF insertion can be enhanced significantly through the generative adversarial network.
OPC (Optical Proximity Correction) has been employed for over decade to address local lithographic printing effects. With the intensive scaling down of the designs as well as the increasing complexity of layout routing, lithographic process is being pushed to its theoretical limit and it has led to continuously shrinking DoF (Depth of Focus). Complex OPC model components are hence included into optical lithography simulation to ensure tolerable CD (Critical Dimension) variation and sustainable DOF of concerned layouts. For example, very complicated segmentation needs to be applied in mask correction, which comes at the cost of long runtime and requires an effective approach to consolidate the adequacy of model components during the flow of correction parameter tuning. In this paper, an approach is demonstrated to improve the accuracy and efficiency of OPC parameter tuning for mask correction. The approach starts with analyzing the target points in post-OPC database to identify those intolerable variations, followed by a pattern similarity grouping for the above intolerable layouts. Then, a concern index is established based on the CD out-of-tolerance ratio, dissection and pattern type for prioritizing the problematic variations. Then the corrective parameters are accordingly optimized to reduce the variation on highly prioritized patterns. During the iteration flow of OPC parameter optimization, the combination of pattern grouping and concern index greatly reduces required optimization iterations for OPC recipe tuning and enhances OPC convergence.
To avoid the dramatically diminishing of lithography process window as the shrink of design rule, the implementation of process-aware optical proximity correction (PWOPC) has been indispensable. The conventional PWOPC is capable of reducing CD variation at off-focus-off-dose conditions for the worst hotspot but some new weak points might be generated due to over compensation from compromising with the worst hotspot. In this paper, a so-called “multiple-step process aware OPC”, was demonstrated for maintaining better process window for all hotspots via damascene metal layer in 43nm half-pitch design. Through isolating the hotspots from the chip layout, different CD tolerances can be applied for the various types of hotspots to avoid the conflicts between different requirements. Increased levels of CD-tolerance could be applied in the multiple-step PWOPC flow for the layout with a great number of weak points. The ultimate aim of the multiple-step PWOPC operation is maintaining sufficient process window for entire layout. The performance comparison was carried out among nominal OPC, conventional PWOPC and multiple-step PWOPC flows for contour CD within appropriate process window, turn around time of layout correction and CD distribution of hotspots.
The accuracy and efficiency of OPC (Optical Proximity Correction) modeling have become paramount important at the
low k1 lithography. However the accuracy of OPC model has to compromise with the efficiency of model calibration
and pattern correction, since the model accuracy is usually improved by using more kernels to represent the model but
the runtime of model setup and pattern correction also increase as kernel count increasing.
A novel decomposition of source kernel for OPC model calibration was presented in this study to maintain the model
accuracy and preserve the OPC runtime at acceptable level. Firstly, the source kernel was decomposed into multiple subsource
kernels and then the magnitude of electric field for each decomposed sub-source was modulated in frequency
domain. Finally, the resultant source can be the combination of many different sub-sources to represent the tool-specific
characteristics. The model accuracy, model stability and modeling runtime were compared among decomposed source,
ideal source and measured source models. The results showed modeling residual RMS error, predictive capability of
decomposed source can be reduced to be comparable to measured source and superior to the ideal source. As for the
modeling efficiency, the decomposed source is up to 5 times faster than the measured source but just few percentages
slower than the ideal source approach.