Process depth of focus analysis has always been an important method for determining semiconductor integrated circuit manufacturability. This is becoming even more apparent as process nodes continue to shrink and more aggressive Resolution Enhancement Technology (RET) techniques are adopted to help retain process latitude. Process window is one of the most important factors in improving yield and reducing production cost. Therefore, pattern verification prior to mask tape-out is essential to save development time, and cost is extremely important.
The concept of focus-sensitive hotspot detection has been recently introduced using a Manufacturing Sensitivity Model (MSM). As the MSM interacts with the pattern, the model produces output that judges the quality of the through-process correction in a single piece of interpreted data. The MSM output can then be readily analyzed to find process sensitive patterns.
In this study, we will apply a process focus sensitivity detection algorithm to various designs using Focus Sensitive Model (FSM). The results will be compared to conventional depth of focus analysis techniques. The goal is to understand the relationship between the focus sensitivity and the CD error variations. This will be used to understand if focus-sensitive hotspot detection using FSM can be applied for verifying RET process qualities.
As semiconductor manufacturing nodes march towards increasingly aggressive process nodes, the features that can be manufactured on a silicon wafer are becoming more and more constrained. These constraints are arising from the need for manufacturing process margin, the result of which is improved yields and wafer throughput. For less aggressive process nodes, these constraints have been transferred between the design and manufacturing communities using tables of design rules. However, as process nodes march forward, these are rules are getting complex and unmanageable. A better methodology to communicate design rules is to build a model of the manufacturing process for use by the design team. This model can then be used to analyze a piece of layout for manufacturing robustness, and allow the design to make informed layout revisions. Design rules encompass effects due to many manufacturing processes including exposure, registration, etch, reticle construction, electro migration, etc. In order to create useful design rules, all of these processes must be understood and combined into a set of process rules. In order to reduce the complexity of the design rules table, a process model may be applied in complex pattern configurations. This study will seek to understand the definition of complex configurations for photolithography design rules, and it will attempt to demonstrate the usefulness of model-based design rules.
MEEF (Mask Error Enhancement Factor) has become a critical factor in CD uniformity control since optical lithography process moved to sub-resolution era. A lot of studies have been done by quantifying the impact of the mask CD (Critical Dimension) errors on the wafer CD errors1-2. However, the benefits from those studies were restricted only to small pattern areas of the full-chip data due to long simulation time. As fast turn around time can be achieved for the complicated verifications on very large data by linearly scalable distributed processing technology, model-based lithography verification becomes feasible for various types of applications such as post mask synthesis data sign off for mask tape out in production and lithography process development with full-chip data3,4,5. In this study, we introduced two useful methodologies for the full-chip level verification of mask error impact on wafer lithography patterning process. One methodology is to check MEEF distribution in addition to CD distribution through process window, which can be used for RET/OPC optimization at R&D stage. The other is to check mask error sensitivity on potential pinch and bridge hotspots through lithography process variation, where the outputs can be passed on to Mask CD metrology to add CD measurements on those hotspot locations. Two different OPC data were compared using the two methodologies in this study.
Gate CD (Critical Dimension) control is an important factor in determining semiconductor manufacturing yield. Therefore, its verification prior to mask tape-out is essential to save development time and cost. Not only is fatal-error detection required to ensure high yield, tight CD control in the gate region is equally critical in sub-micron IC manufacturing.
As fast turn around time is achieved for very large data through scalable distributed processing, model-based lithography verification has been utilized for checking the post mask synthesis data quality before mask tape out and RET/OPC process development.
In this paper, we introduce a comprehensive methodology to study and qualify Poly mask layer using a model based lithography verification tool. This flow will include CD checks on both gate-width and gate- length dimensions. Gate CD distribution plots on the poly layer will be done across a complete range of target CDs in order to investigate wafer CD uniformity errors on full-chip level under various process conditions. In addition, the traditional edge-placement detection will be discussed and compared to absolute CD verification process.
Contact and via layers are becoming more critical than before from lithography point of view due to the fact that the contact and via sizes for advanced devices are falling into deep sub-wavelength ranges. In this study, we will demonstrate several different methodologies for contact and via CD variation check and contact/metal overlay checks on the post-opc data using a model based verification software platform. Our study reveals that the full chip verification for the contact and via layers is necessary
achievable to guarantee the mask data quality and to prevent catastrophic pattern errors resulting from improper OPC corrections. Good scalability of the software methodology and platform makes it possible to do the full chip verification with reasonable turn around
Model based full-chip lithography verification has been proven as a mask sign off solution to prevent patterning failures caused by design/OPC (Optical Proximity Correction) before mask data tape out. Furthermore, as the fast turn around time is achieved through scalable distributed processing for very large data after mask synthesis conversion such as assist feature and OPC, model-based full-chip verification can take advantages of RET (Resolution Enhancement Technique)/OPC recipe development. In previous studies, we introduced the full-chip verification methodologies for mask sign off flow in production and for RET/OPC optimization flow in process development stage for sub-wavelength lithography processes in general.
In this paper, we demonstrated the layer-specific verifications for critical layers for 65nm lithography process development. For poly layer, we performed various types of checks such as fatal pinch/bridge hotspots, CD variations, line-end/space-end errors, assist feature printability, MMEF (Mask Error Enhancement Factor) and geometrical (Mask Rule/structural) checks considering the mask manufacturing constraints. We compared hyper NA (Numerical Aperture)illumination using immersion lithography with the double expose alternating PSM (Phase Shift Mask) lithography. For metal layer, various full-process window coverage verification methodologies were discussed.