Grayscale lithography has become a common technique for three dimensional structuring of substrates. In order to make the process useful for manufacturing of semiconductor and in particular optoelectronic devices, high reproducible and uniform final film thicknesses are required. Simulations based on a calibrated resist model are used to predict customized process parameters from pixel layout to 3d substrate patterning. Multiple, arbitrary resist heights are reached by using i-line lithography. Scalable and uniform transfer of discrete step heights into oxide are realized by multiple alternating high selective resist and oxide (MASO) etch. Requirements and limitations of reliable 3D film thickness and uniformity control within a CMOS fabrication environment are being discussed.
In this paper we describe an approach for the realization of 3D resist patterns for implant applications, highlighting the opportunities of controlling doping depth and profiles and their influence on device parameters. We choose a grayscale litho process, where the 3D structuring of the photoresist is done by a spatially variable exposure. Pixilated grayscale mask structures are defined to achieve the desired 3D resist patterns by locally variable transmittance values. The variable transmittance values result in different resist film thicknesses after development. Up to 20 different resist film thicknesses are obtained within a single exposure shot. This enables spatial patterning of the implant depth and accordingly various novel approaches for device optimization.
The fabrication of semiconductor devices can be complicated by various defectivity issues with respect to fabrication
process steps, their interactions, the used materials and tool settings. In this paper we will focus on a defect type, called
spire or cone defect. This conducting defect type is very common in the shallow trench isolation (STI) process. The
presence of a single defect can be responsible for a device breakdown or reliability problems, which will result in a
serious impact on the competitive edge for a product qualification. Spire defects, which can only be detected after etch,
are observed on all our technology nodes using 248nm or 193nm exposure techniques.
Bottom Anti-Reflection Coatings (BARC) impurities are considered to be the main root cause for the formation of spire
defects. Therefore we focused our efforts on chemical filtration of the BARC material and related solvents, the usage of
different BARC materials and the influence of the subsequent etch steps in order to reduce or overcome the spire defect
problem. In this paper we will discuss the effectiveness of different filter materials, pore sizes and different BARC
materials (organic and dielectric BARC) with respect to defect analysis and lithographic performance.
Among available lithography resolution enhancement techniques the Selective Inverse Lithography (SILT) approach
recently introduced by authors  has been shown to provide the largest process window on lower-NA exposure tools
for 65nm contact layer patterning. In present paper we attempt to harness the benefits of source mask optimization
(SMO) approach as part of our hybrid RET. The application of source mask optimization techniques further extends the
life-span of lower-NA 193nm exposure-tools in high volume manufacturing. By including SMO step in OPC flow, we
show that model-based SRAF solution can be improved to approach SILT process variation (PV) band performance.
Additionally to OPC, the complexity of embedded flash designs requires a high degree of exposure tool matching and a
lithography process optimized for topographically different logic and flash areas. We present a method how SMO can be
applied to scanner matching and topography-related optimization.
In order to fulfill the demands of further shrinkage of our mature 90nm logic litho technologies under the constraints of
costs and available toolsets in a 200mm fab environment, a project called "Push to the Limits" was started. The aim ís
to extend the lifetime and capabilities of existing dry 193nm litho toolsets with medium to low numerical aperture,
coupled with the availability of materials and processes which were known to help up CD miniaturization and to shrink
the 90nm logic litho process as far as possible. To achieve this, various options were explored and evaluated, e.g.
optimization of illumination conditions, evaluation of new materials, usage of advanced RET techniques (OPC, LfD,
DfM and ILT) and resolution enhancement by chemical shrink (RELACS®). In this project we demonstrate how we were
able to extend our existing 90nm technology capability, down close to 65nm node litho requirements on most critical
layers. We present overall result in most critical layer generally and specifically on most difficult layer of contact.
Typical contact litho target at 100nm region was enabled, while realization of 90nm ADI target is possible with addition
of new process materials.
Tests of several high contrast g- and i-line resists furnish data with respect to the resolution limit focus and exposure latitudes thermal stability and Dill parameters. A g. -line stepper of NA 0. 48 and an i-line stepper of NA 0. 40 were primarily used for exposure to a minor extent a g-line stepper of NA 0. 55. The contributions to the focus budget available under production conditions are discussed. SAMPLE simulations extending NA to 0. 60 in the gline and 0. 50 in the i-line case give latitude trends to be expected in the near future. 1.