In the past few decades, leading edge logic technology scaling has been the main driver for semiconductor metrology developments. As traditional device scaling is slowing down, the semiconductor industry is focusing also on heterogeneous integration approaches, which leverage advanced packaging technologies to integrate devices designed and manufactured separately using the most suitable process technology for each device. Heterogeneous integration presents significant metrology challenges, which are different from what is encountered at the logic device level in terms of materials and specifically dimensions. Large-scale 3D structures need to be characterized with unprecedented accuracies and advanced optical techniques play a pivotal role. In this paper, some metrology challenges in heterogeneous integration are introduced and discussed related to TSV characterization including depth and reveal height, wafer bonding measurements, and dimensional and overlay metrology for processing leading to bump receivers and bump formation. Current capabilities utilizing various imaging and interferometry techniques are presented and their limitations discussed.
Comprehensive through-silicon-via (TSV) characterization, including grind side measurements, is critical to ensure device reliability in chiplet technology. Here we report on TSV metrology using spectral interferometry (SI), which is used to acquire absolute phase information of polarized and broad-band light interacting with a sample. This phase information can be translated into the optical path length of the partial beams traveling within the structure. We utilize the spatial separation of peaks related to light reflected from the top surface and the surface of interest to directly measure the TSV depth after reactive ion etching as well as the reveal height on the grind side, without modeling and even in the presence of multilayers or surrounding patterning. Polarization-dependent SI measurements enable the quantification of asymmetry at the bottom of the TSVs not visible in top-down CD measurements. SI is robust and fast and unveils novel information in TSV metrology not accessible with established in-line metrology techniques.
This paper demonstrates the successful lab-to-fab transition of dynamic secondary-ion mass spectrometry (SIMS). In comparison to traditional lab SIMS, the in-line version is optimized for automated wafer and measurement sequence handling and high throughput measurements in small areas. Key advantages are fast turn-around time, reduced scrap, increased yield, and the measured wafer can continue processing in the manufacturing line. The benefits of in-line SIMS in the production environment are demonstrated for several use cases: matching and monitoring the long-term stability of epitaxy tools on monitor wafers, process optimization and monitoring of epitaxial Si and SiGe layers on blanket and patterned wafers with blanket metrology targets, measurement of implant and dopant profiles on blanket and patterned wafers, and characterization of the Ge and B diffusion in multi-layer stacks stimulated by high-temperature annealing. Additionally, the characterization of the source/drain epitaxy in a fully integrated nanosheet gate-all-around transistor architecture is demonstrated and discussed. The results are compared to off-line lab SIMS and alternative methods where available.
The semiconductor industry has witnessed a fast progression of spectroscopic ellipsometry (SE) techniques aimed at resolving a plethora of complex device characterizations on a nanometric scale. The Mueller Matrix (MM) methodology coupled with rigorous coupled-wave analysis (RCWA) has offered an unprecedented power of investigation and analysis of diverse critical dimensions (CDs), especially when applied to gate-all-around (GAA) structures, as it helps increase the useful spectral signals of the often geometrically buried CDs. However, the sensitivity to the CDs can be often screened by other parameters, hampering the precision and accuracy of the measurement. Combining the most sensitive MM elements has therefore become a critical step of scatterometry critical dimension (SCD) metrology. Driven by the rapid developments of Machine Learning (ML) algorithms, we propose a versatile ellipsometry methodology that overcomes poor sensitivity and increases accuracy through a novel principal component analysis (PCA) method of the ML training algorithm with RCWA assistance. Furthermore, our methodology introduces a new ML training concept based on reference data statistics, rather than raw reference. Our approach has been validated with reference data and proved successful in monitoring GAA sheet-specific indent. The proposed methodology paves the way to measuring low sensitivity CDs with highly accurate, noise-reduced and robust ML-based physical SCD models for any logic and memory application.
In an earlier publication, we evaluated simulation methods to explore overlay performance implications when a highNumerical Aperture (high-NA) Extreme Ultra Violet (EUV) exposure is mixed and matched with a 0.33NA EUV full field exposure. The present contribution goes beyond the method description and aims to quantify the overlay performance impact in such a mix and match case, giving insight into the influence of different sets of overlay corrections. To this aim, the Mont Carlo engine has been updated to accommodate overlay corrections with up to 57 parameters. Since high-NA EUV is not yet available, typical overlay correction terms from IBM’s 0.33NA EUV tool have been used to approximate a realistic image placement error fingerprint for our simulations. As a result, we demonstrate the benefit of various overlay correction sets, and the detrimental effect when using different masks for top and bottom half fields. Such information can also help to infer design layout placement decisions to avoid hot spot regions.
A comprehensive picture of the stress evolution within arrays of through-silicon-vias (TSV) is developed using in-line Raman spectroscopy. A set of wafers with different TSV geometries and metal seed liner thicknesses is exposed to various annealing conditions. Monitoring the Si-Si phonon mode shift between the vias, the influence of via geometries and processing conditions on the stress in the Si substrate is characterized non-destructively. Compressive stress is found in close proximity to the TSVs post Cu fill, as expected. However, for arrays with small TSV pitches, the substrate does not fully relax in the space between the vias, but rather tensile stress accumulates within the arrays. This inter-via stress increases with decreasing TSV pitch, accumulates towards the center of the arrays, and strongly depends on the annealing conditions. High resolution Raman maps within the arrays reveal the full picture of stress distribution in the TSV arrays. By using different excitation wavelengths, the variation of the stress with depth in the Si wafer is probed. The findings demonstrate the value of in-line access to process-dependent stress information. This knowledge helps to define design ground rules for highest device performance or to maximize the useable area on the wafer for logic devices.
A spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective analyses of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows for focusing on parameters of interest through dramatically simplified optical modeling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are monitored discussed: (i) the critical dimensions (CDs) of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) the CDs of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy. Furthermore, it was shown that machine learning models trained with VTS filtered data can converge to a robust solution with a smaller dataset compared with models training with traditional scatterometry data.
Extreme Ultraviolet (EUV) lithography has gained maturity and is now the de facto leading edge patterning technology for advanced nodes beyond 7nm. Looking forward, the industry is exploring how to push the resolution even further. A high NA EUV scanner promises to increase the numerical aperture to capture larger diffraction orders enabling resolution improvement. The desire to use existing mask infrastructure with the anamorphic high NA projection lens project results in a half-field on wafer as compared to the currently available low NA EUV scanner. Once the high NA scanner is available, integrated devices will be manufactured with mix and match full-field and half-field lithography. This will bring its own set of challenges from an overlay error minimization standpoint, as half-field and full-field will not share the same center of gravity. Given the fact that overlay models are well known and that the high NA EUV scanner is not yet commercially available we took the approach to emulate the process through computer Monte Carlo simulations.
This paper will explain the methods and assumptions used for the Monte Carlo simulation and explore how the mix and match affect the overlay correctable and none-correctable errors
Magnetoresistive random-access memory (MRAM) technology and recent developments in fabrication processes have shown it to be compatible with Si-based complementary metal oxide semiconductor (CMOS) technologies. The perpendicular spin transfer torque MRAM (STT-MRAM) configuration opened up opportunities for an ultra-dense MRAM evolution and was most widely adapted for its scalability. Insertion of STT-MRAM in the back end of line (BEOL) wiring levels has many advantages, including density, latency, and endurance with the promise of being comparable to performance of dynamic random access memory technology (DRAM). There are several important parameters at multiple process steps which require precise metrology for STT-MRAM integration. Inline metrology of the magnetic tunnel junction (MTJ) pillar is vital to calibrate the magnetic read/write performance parameters. This work discusses various challenges to monitor critical process steps for integrating STT-MRAM in advanced CMOS technologies and key metrology solutions are presented. To precisely predict MRAM junction resistance early in the process flow, a machine learning model was developed using scatterometry spectra collected after MTJ pillar formation and corresponding resistance data from the end of line electrical test. This machine learning model utilizes metrology data from the pillar formation process and can predict accurate device resistance values. Additionally, carefully monitoring the required planarization process of an interlayer dielectric deposited after the MTJ pillar formation is critical to avoid subsequent defects. Several modelling techniques are discussed and a new spectral interferometry-based technique, vertical travelling scatterometry (VTS), is demonstrated as a solution for measurements on fully integrated device areas.
KEYWORDS: Metrology, Semiconducting wafers, Scatterometry, Optical filters, Dielectrics, Data modeling, Back end of line, Front end of line, Chemical mechanical planarization, Transmission electron microscopy
In this work, a novel spectral interferometry technique called vertical travelling scatterometry (VTS) is introduced, demonstrated, and discussed. VTS utilizes unique information from spectral interferometry and enables solutions for applications that are infeasible with traditional scatterometry approaches. The technique allows for data filtering related to spectral information from buried layers, which can then be ignored in the optical model. Therefore, using VTS, selective measurements of the topmost part of an arbitrarily complex stack are possible within a single metrology step. This methodology helps to overcome geometrical complexities and allows focusing on parameters of interest through dramatically simplified optical modelling. Such model simplifications are specifically desired for back-end-of-line applications. Three examples are discussed in this paper: monitoring (i) critical dimensions of a first metal level on top of nanosheet gate-all-around transistor structures, (ii) the thickness of an interlayer dielectric above embedded memory in the active area, and (iii) critical dimensions of trenches on top of tall stacks in the micrometer range comprising many layered dielectrics. It was found that, in all three cases, data filtering through VTS allowed for a simple optical model capable of delivering parameters of interest. The validity and accuracy of the VTS solution results were confirmed by extensive reference metrology obtained by traditional scatterometry, scanning electron microscopy, and transmission electron microscopy.
Over the past several years, stacked nanosheet gate-all-around (GAA) transistors captured the focus of the semiconductor industry and have been identified as the lead architecture to continue logic complementary metal-oxide-semiconductor scaling beyond 5 nm node. The fabrication of GAA devices requires specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology progresses through research and development cycles and is poised to transition to manufacturing, there are many opportunities and challenges that still remain for in-line metrology. Especially valuable are measurement techniques that are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact on the frequency of cycles of learning. More than previous technologies, then, nanosheet technology may be when some offline techniques transition from the lab to the fab, as certain critical measurements need to be monitored in real time. Thanks to the computing revolution the semiconductor industry enabled, machine learning has begun to permeate in-line disposition, and hybrid metrology systems continue to advance. Of course, metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness, pitch walk, and defectivity continue to be managed. We review related prior studies and advocate for future metrology development that ensures nanosheet technology has the in-line data necessary for success.
In-line Raman spectroscopy for compositional and strain metrology throughout front-end-of-line (FEOL) manufacturing of next-generation gate-all-around nanosheet field-effect transistors is presented. Thin and alternating layers of fully strained pseudomorphic Si(1 − x)Gex and Si were grown epitaxially on a Si substrate and subsequently patterned. Intentional strain variations were introduced by changing the Ge content (x = 0.25, 0.35, 0.50). Polarization-dependent in-line Raman spectroscopy was employed to characterize and quantify the strain evolution of Si and Si(1 − x)Gex nanosheets throughout FEOL processing by focusing on the analysis of Si-Si and Si-Ge optical phonon modes. To evaluate the accuracy of the Raman metrology results, strain reference data were acquired by non-destructive high-resolution x-ray diffraction and from destructive lattice deformation maps using precession electron diffraction. It was found that the germanium-alloy composition as well as Si and Si(1 − x)Gex strain obtained by Raman spectroscopy are in very good agreement with reference metrology and follow trends of previously published simulations.
High NA EUV lithography will offer single exposure patterning for pitches below 28nm, simplifying process flows. However, overlay error complexity will increase. Specifically, a semiconductor build will require use of both high NA EUV tools that can only expose half the field size of low NA EUV and optical tools. This means that to achieve full productivity on the low NA EUV and optical tools used, a semiconductor build using these tools will need to minimize overlay error back to a scanner map exposed with the high NA EUV tool that has twice the number of exposures. Overlay error minimization on full field tools takes advantage of keeping exposure maps constant between different layers so that scan direction and step direction are maintained. This is not possible when using a high NA EUV tool in a semiconductor build unless the number of scans on the low NA and optical tools are doubled, thus decreasing the productivity on those tools. Having a full field minimize overlay error back to two half fields results in new required overlay controls between the two half fields to achieve low overlay error. In particular, stitch overlay control for the half field exposures can be very helpful to achieving good overlay error between a layer exposed with full field exposure map and a layer exposed with a half field exposure map. To get early learning on these effects, we designed a test reticle with a unique “figure 8” black border that allows step plans to be exposed with either half or full field exposures. To get rapid learning the reticle is designed to take advantage of resist-to-resist overlay targets that engage with each other when there is a programed 180 um step delta between the two exposures. The effects of order of exposures as well as scan and step direction differences between the half field and full field step plans are investigated.
In this work, the novel enhancement to multichannel scatterometry data collection, Spectral Interferometry, is introduced and discussed. The Spectral Interferometry technology adds unique spectroscopic data by providing absolute phase information. This enhances metrology performance by improving sensitivity to weak target parameters and reducing parameter correlations. Spectral Interferometry enhanced OCD capabilities were demonstrated for one of the most critical and challenging applications of gate-all-around nanosheet device manufacturing: lateral etching of SiGe nanosheet layers to form inner spacer indentations. The inner spacer protects the channel from the source/drain regions during channel release and defines the gate length of the device. Additionally, a methodology is presented, which enables reliable and reproducible manufacturing of reference samples with engineered sheet-specific indent variations at nominal etch processing. Such samples are ideal candidates for evaluating metrology solutions with minimal destructive reference metrology costs. Two strategies, single parameter and sheet-specific indent monitoring are discussed, and it was found that the addition of spectroscopic information acquired by Spectral Interferometry improved both optical metrology solutions. In addition to improving the match to references for single parameter indent monitoring, excellent sheet-specific indent results can be delivered
In-line Raman spectroscopy for compositional and strain metrology throughout front-end-of-line manufacturing of next generation stacked gate-all-around nanosheet field-effect transistors is presented. Thin and alternating layers of fully strained pseudomorphic Si(1-x)Gex and Si were grown epitaxially on a Si substrate and subsequently patterned. Intentional strain variations were introduced by changing the Ge content (x = 0.25, 0,35, 0.50). Polarization-dependent in-line Raman spectroscopy was employed to characterize and quantify the strain evolution of Si and Si(1-x)Gex nanosheets throughout front-end-of-line processing by focusing on the analysis of Si-Si and Si-Ge optical phonon modes. To evaluate the accuracy of the Raman metrology results, strain reference data were acquired by non-destructive high-resolution x-ray diffraction and from destructive lattice deformation maps using precession electron diffraction. It was found that the germanium-alloy composition as well as Si and Si(1-x)Gex strain obtained by Raman spectroscopy are in excellent agreement with reference metrology and follow trends of previously published simulations.
Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of GAA devices requires new specific integration modules. From very early processing points, these structures require complex metrology to fully characterize the three-dimensional parameter set. As the technology continues through research and development cycles and looks to transition to manufacturing, there are many opportunities and challenges remaining for inline metrology. Especially valuable are measurement techniques which are non-destructive, fast, and provide multi-dimensional feedback, where reducing dependencies on offline techniques has a direct impact to the frequency of cycles of learning. More than previous nodes, then, this node may be when some of these offline techniques jump from the lab to the fab, as certain critical measurements need to be monitored realtime. Thanks to the compute revolution this very industry enabled, machine learning has begun to permeate inline disposition, and hybrid metrology systems continue to advance. Metrology solutions and methodologies developed for prior technologies will also still have a large role in the characterization of these structures, as effects such as line edge roughness (LER), pitchwalk, and defectivity continue to be managed. This paper reviews related prior studies and advocates for future metrology development that ensures nanosheet technology has the inline data necessary for success.
A methodology of obtaining the local critical dimension uniformity of contact hole arrays by using optical scatterometry in conjunction with machine learning algorithms is presented and discussed. Staggered contact hole arrays at 44 nm pitch were created by EUV lithography using three different positive-tone chemically amplified resists. To introduce local critical dimension uniformity variations different exposure conditions for dose and focus were used. Optical scatterometry spectra were acquired post development as well as post etch into a SiN layer. Reference data for the machine learning algorithm were collected by critical dimension scanning electron microscopy (CDSEM). The machine learning algorithm was then trained using the optical spectra and the corresponding calculated LCDU values from CDSEM image analyses. It was found that LCDU and CD can be accurately measured with the proposed methodology both post lithography and post etch. Additionally, since the collection of optical spectra post development is non-destructive, same area measurements are possible to single out etch improvements. This optical metrology technique can be readily implemented inline and significantly improves the throughput compared to currently used electron beam measurements.
As development of stacked Nanosheet Gate All-Around (GAA) transistor continues as the candidate technology for future nodes, several key process points remain difficult to characterize effectively. With the GAA device strategy, it is critical to have an inline solution that can provide a readout of physical dimensions that have an impact on the threshold voltage (VT) and yield. Metrology challenges for obtaining these metrics arise from increasingly dense arrays coupled with both high aspect ratios, high numbers of correlated parameters, and increasingly complex 3D geometries. Large area metrology structures can be used for 3D parameters’ process monitoring through techniques such as scatterometry and xray diffraction (XRD) which deliver averaged results over that area, but variation impacting specific devices cannot currently be understood without destructive cross-section. Prior work to characterize the dimensions of these GAA devices has primarily featured optical metrology, X-ray metrology, and critical-dimension scanning electron microscopy (CDSEM), but these techniques have their own challenges at the critical process points. Atomic force microscopy (AFM) had not been utilized due to the aspect ratios and small trench widths which were inaccessible to conventional techniques. However, due to recent advances in scanning and novel probe technologies, AFM is well-suited now to solve these local, three-dimensional challenges. Through this study, we demonstrate AFM characterization of a key process point in the GAA process flow for multiple structures with varying channel lengths, after epitaxial (epi) growth along the Si sidewall. The AFM scan results are compared to CDSEM images for top-down corroboration of topography and to other reference metrology for height correlation. The impact of measured variations in epi height to device performance is also reviewed.
EUV resist characterizations for line and space patterning as a function of dose and illumination conditions for varying pitches down to 28 nm are discussed. The unintentional resist line top loss (LTL) after development has been monitored and analyzed for all experimental conditions. Furthermore, line top roughness (LTR) is introduced, which is a 3 stochastic metric characterizing in-plane roughness related to the top of the resist lines. The main characterization technique employed for this study is atomic force microscopy (AFM) with novel probing algorithms as well as novel tips with diameters down to 5 nm and aspect ratios of 10:1. Additionally, results acquired by critical dimension scanning electron microscopy and optical critical dimension scatterometry are presented. It was found that the unintentional LTL is resist- and pitch-dependent and can be higher than 9 nm at 16 nm half-pitch but does not correlate with line break defect density results. However, LTR measurements of small area scans at dense line/space pitches may be used to draw conclusions about line break defect densities and hence yield. The resist specific metrics, LTR and LTL, allow for fast and early-on evaluation of new chemical formulations and help to forecast pitch- and dose-dependent performance. Furthermore, the results can be used to improve resist model accuracy for optical proximity correction calculations.
The effects of EUV scanner actuated overlay corrections on image fidelity are discussed. Intrafield overlay corrections are implemented by reticle and/or wafer stage modulations during the exposure scan, which may lead to stage desynchronizations. The impact of such a mismatch on imaging is comparable to stage vibrations, which contribute to image blurring commonly known as image fading. For this study, deliberate stage desynchronizations were introduced by means of an asymmetric image rotation and effects on image fidelity qualitatively evaluated by pattern shift response (PSR) metrology. The PSR targets studied are blossom-style marks with asymmetric petal designs that transform process variations to a virtual pattern shift, which can be measured by conventional image-based overlay metrology. Corroborating as well as quantitative results were acquired by analyses of line width roughness. It was found that stage desynchronizations induced by overlay corrections can significantly degrade image fidelity starting with increased line width roughness up to a total pattern failure of linewidths relevant to current and future technology nodes. PSR metrology shows excellent capabilities to characterize relative image fidelity as well as across slit distortions and is therefore a suitable monitoring technique for on-wafer performance.
As device scaling continues, controlling defect densities on the wafer becomes essential for high volume manufacturing (HVM). One type of defect, the non-selective SiGe nodule, becomes more difficult to control during SiGe epitaxy (EPI) growth for p-type field effect transistor (pFET) source and drain. The process window for SiGe EPI growth with low nodule density becomes extremely tight due to the shrinking of contact poly pitch (CPP). Any tiny process shift or incoming structure shift could introduce a high density of nodules, which could affect device performance and yield. The current defect inspection method has a low throughput, so a fast and quantitative characterization technique is preferred for measuring and monitoring this type of defect.
Scatterometry is a fast and non-destructive in-line metrology technique. In this work, novel methods were developed to accurately and comprehensively measure the SiGe nodules with scatterometry information. Top-down critical dimension scanning electron microscopy (CD-SEM) images were collected and analyzed on the same location as scatterometry measurement for calibration. Machine learning (ML) algorithms are used to analyze the correlation between the raw spectra and defect density and area fraction. The analysis showed that the defect density and area fractions can be measured separately by correlating intensity variations. In addition to the defect density and area fraction, we also investigate a novel method – model-based scatterometry hybridized with machine learning capabilities – to quantify the average height of the defects along the sidewall of the gate. Hybridizing the machine learning method with the model-based one could also eliminate the possibility of misinterpreting the defect as some structural parameters. Furthermore, cross-sectional TEM and SEM measurement are used to calibrate the model-based scatterometry results. In this work, the correlation between the SiGe nodule defects and the structural parameters of the device is also studied. The preliminary result shows that there is strong correlation between the defect density and spacer thickness. Correlations between the defect density and the structural parameters provides useful information for process engineers to optimize the EPI growth process. With the advances in the scatterometry-based defect measurement metrology, we demonstrate such fast, quantitative, and comprehensive measurement of SiGe nodule defects can be used to improve the throughput and yield.
Although lens aberrations in EUV imaging systems are very small, aberration impacts on pattern placement error and overlay error need to be carefully investigated to obtain the most robust lithography process for high volume manufacturing. Instead of focusing entirely on pattern placement errors in the context of a single lithographic process, we holistically study the interaction between two sequential lithographic layers affected by evolving aberration wavefronts, calculate aberration induced overlay error, and explore new strategies to improve overlay.
Surface-enhanced Raman scattering (SERS) is drawing increasing interest in fields such as chemical and biomolecular sensing, nanoscale plasmonic engineering and surface science. In addition to the electromagnetic and chemical enhancements in SERS, several studies have reported a “back-side” enhancement when nanostructures are excited through a transparent base rather than directly through air. This additional enhancement has been attributed to a local increase in the electric field for propagation from high to low refractive index media. In this study, Mueller matrix ellipsometry was used to derive the effective optical constants of Ag nanostructures fabricated by thermal evaporation at oblique angles. The results confirm that the effective optical constants of the nanostructured Ag film depart substantially from the bulk properties. Detailed analysis suggests that the optical constants of the nano-island Ag structures exhibit uniaxial optical properties with the optical axis inclined from the substrate normal towards the deposition direction of the vapour flux. The substrates were functionalized with thiophenol and used to measure the wavelength dependence of the additional SERS signal. Further, a model based on the Fresnel equations was developed, using the Ag film optical constants and thickness as determined by ellipsometry. Both experimental data and the model show a significant additional enhancement in the back-side SERS, blue shifted from the plasmon resonance of the nanostructures. This information will be useful for a range of applications where it is necessary to understand the effective optical behaviour of thin films and in designing miniaturized optical fibre sensors for remote sensing applications.
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