Proceedings Article | 10 October 2019
KEYWORDS: Photomasks, Extreme ultraviolet, Optical lithography, Semiconducting wafers, Reticles, Extreme ultraviolet lithography, Scanners, Polishing, Computer simulations, Surface finishing
Extreme ultraviolet (EUV) lithography is entering high volume manufacturing, and these lithography tools are expected to be the enabling technology for reaching the next several lithography nodes. With each successive node, features will continue to shrink following Moore’s law, and the relative error contributions from flatness-related topographies will increase. Photomask blank manufacturers are responding to increasingly challenging flatness specifications with more dynamic methods to mitigate any non-flat surface characteristics and thus their contribution to the final on-wafer error. Such methods include iterative dynamic polishing, write compensation, and scanner-related corrections, all of which utilize high-resolution interferometric measurements to provide feedback on the reticle's shape, which in turn can be used to calculate the reticle's contribution to overlay and image placement at wafer. As the industry progresses through each node, these flatness requirements restrict to a point where the production of photomask blanks is extremely challenging to achieve, requiring reticles with single-digit nanometer (peak to valley) flatness. The challenges associated with producing blanks to this level drive up production time and product costs. To alleviate some of these constraints, ASML has recommended the use of four functional, reticle flatness key performance indicators (KPIs), which characterize a blank’s contributions to the overall process window, including any relief provided by in-scanner correction methods, and allow for a straight-forward framework to identify which geographic features are “passable” and which are "prohibitive" to the ultimate overall system requirements. The calculation and application of the KPIs take into consideration numerous factors of the reticle's production and use, including their topographic features, the chucking mechanism used in the scanner, and the illumination of the scanner to best simulate the final on-wafer results. Previous publications explored the application of these KPIs to representative reticle data sets, both physical and simulated, using the architecture of the ASML NXE:3400 EUV platform, and explored what level of relief they may provide for reticle flatness requirements. In this paper, we again explore the application of ASML’s KPIs, now using the next generation 0.55 NA EUV scanner architecture, the ASML EXE:5000, to ascertain what level of relief or complexity may be required of blank polishers in order to meet the process window requirements of future nodes. In this fashion, we are then able to determine what general flatness-related guiding principles will be required for next generation blanks, and whether these principles will require additional process development or innovation.
