Silicon-on-insulator (SOI) substrate technology has been the defining foundation of silicon photonics integrated circuits over the last 20+ years, fostering its commercial success in datacenter interconnects and promoting widespread adoption for high-speed optical transceiver products. More recently, novel applications could also leverage the silicon photonics toolset and ecosystem maturity to target newer, expanding markets, including consumer sensing for healthcare monitoring devices, LiDAR devices for the automotive, as well as optics-based advanced quantum computing and neural networks.
In such dynamic context, Photonics-SOI substrates design and the underlying Smart-Cut process need to relentlessly adapt in order to meet the evolving requirements of end-products and applications specifications, while addressing industrial high-volume manufacturability, high fabrication yields, cost-effectiveness, and related quality constraints. More specifically, the need for growing aggregated bandwidth density at low power dissipation in transceivers products as well as the integration of increasingly complex optical functions for sensing applications, are driving towards more stringent requirements in terms of top silicon layer within-wafer and wafer-to-wafer uniformity, atomic-scale surface roughness, low defect density and improved crystalline material quality. In this paper, the authors report on technological advances in the 300-mm Photonics-SOI process, while benchmarking these on a 300-mm silicon photonics multi-project wafer (MPW) process run. Notably, an extensive set of silicon photonics devices and circuits will be fabricated on a matrix of 220-nm-thick 2-μm-buried oxide Photonics-SOI substrates using different Smart-Cut process windows, with optical characterization data and device performance supporting the ultimate choice of substrate technology for silicon photonics process design kits on thin-SOI platforms.
This numerical study focused on the errors that can occur when ellipsometric spectroscopic scatterometry programs are used for critical dimension (CD) control and other significant geometrical parameters. The role of the number of wavelengths, the measurements noise and the spectral range is analyzed in terms of CD precision. Conversely, an important part is devoted to the effect of a bad shaping modelling of the lines (corner rounding, foot and notch effects) and bad characterization of the index. We show that the scatterometry technique is very resistant to measurement noise, even for a small number of wavelengths, although the spectral range has an important role on the CD calculation. We also give quantitative data about the accuracy needed on refractive index of the diffracting
material must. Excepted for profiles with additional feet, the CD found is very close to the original line without geometrical defects (corner rounding and notches).
With the objective to ramp-up 65 nm CMOS production in early 2005, preliminary works have to start today to develop the basic technological in order to be correctly prepared. In the absence of commercial advanced 193 nm scanners compatible with these aggressive design rules, electron beam technology was employed for the realization of a first 6-T SRAM cell of a size of 0.69 μm2. This paper highlights the work performed to integrate E-beam lithography in this first 65 nm CMOS process flow.
A key enabler to a successful process development and to the device functionality is the introduction of a proper metrology framework, consisting in the selection of the 'correct' tool class for the proposed application on one hand and in the integration of the related measuring procedure into the whole process flow on the other hand. The plan for this work was focused onto the analysis of the main options for critical dimension (CD) measurements targeting to the 65nm technology node, as stated in the International Technology Roadmap for Semiconductors (ITRS) 2001 edition and in the ITRS 2002 update. In order to investigate in deper details the actual status of each selected technique, a list of key characteristics was identified and a comprehensive benchmark performed. Considered techniques include CD-scanning electron microscopy (SEM), CD-scatterometry, CD-atomic force microscopy and 'Combo' approaches. Based upon the data collected during the benchmark phase, suitable procedures to be applied for a proper metrological evaluation of the 65nm node proces development are presented.
Using scatterometry based on Spectroscopic Ellipsometry, a complete study of Gate lithography level measurement on standard products has been conducted. Experiments were done on typical ST batches for 120, 90, and 65 nm nodes. KLA-Tencor SpectraCD SE system is used to collect and analyze line critical dimensions and profiles. A systematic correlation with Scanning Electron Microscope (SEM) is done, completed by a cross section analysis. The study also takes into account lithography defect anlysis using a specific targets with intentionally generated process failures. Our objective is to determine the sensitivity window of such measurment technique to process defect and marginal process conditions. We show that KLA-Tencor SpectraCD allows a full reconstruction of the line profile - as well as the film stack underneath it - with values that are in agreement with production control. Cpm values obtained on products demonstrate that SE based scatterometry fulfils all requirements to be integrated in a production envrionemnt and provides suitable metrology for advanced lithography process monitoring.
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