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This paper will first discuss alternative techniques and methodologies for detection of lithography-related defects, such as scumming and microbridging. These strategies will then be used to gain a better understanding of the effects of material property changes, process partitioning, and hardware improvements, ultimately correlating them directly with electrical yield detractors .
In this paper we will introduce self-alignment based block and cut strategies using multi-color materials integration and show implementation for BEOL trench block patterning. We will present a breakdown of the key unit process challenges that were needed to be resolved for enabling the self-alignment such as: (a) material selection of multi-color approach; (b) planarization of spin on materials; (c) void-free gap fill for high aspect ratio features; and last but not the least, (c) etch selectivity of etching one material with respect to all other materials exposed. Further, we will present a comparison of our new self-alignment approach with standard approaches where we will articulate the advantages in terms of EPE relaxation and mask number reduction. We will conclude our talk with a brief snapshot of the future direction of our EPE improvement strategies and our view on the future of patterning beyond 5nm node for the industry.
In this paper, we review key defectivity learning required to enable 7nm node and beyond technology. We will describe ongoing progress in addressing these challenges through track-based processes (coating, developer, baking), highlighting the limitations of common defect detection strategies and outlining methodologies necessary for accurate characterization and mitigation of blanket defectivity in EUV patterning stacks. We will further discuss defects related to pattern collapse and thinning of underlayer films.
With this larger CD starting point, the burden of shot noise changes significantly and the ability for higher speed resist formulations to be used is enabled. Further resist candidates that may have not met the resolution requirements for EUV can also be evaluated. This implies a completely different operational set-point for EUV resist chemistry where the relaxation of both LER and CD together combined, give the resist formulation space a new target when EUV is used as a SADP tool. Post processing mitigation of LWR is needed to attain the performance of the final 16nm half pitch target pattern to align with the industry needs.
If the original process flow at an 85W projected source power would run in the 50WPH range, then the flow proposed here would run in the <120WPH range. Although it is a double patterning technology, the proposed process still only requires a single pass through the EUV tool, This speed benefit can be used to offset the added costs associated with the double patterning process. This flow can then be shown to be an enabling approach for many EUV applications.
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