Mr. David Laidler Profile

David Laidler

Researcher Advanced Lithography at imec

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Author

Publications (35)

Proceedings Article | 28 March 2017 Paper

Wafer-shape based in-plane distortion predictions using superfast 4G metrology

Leon van Dijk, Jeffrey Mileham, Ilja Malakhovsky, David Laidler, Harold Dekkers, Sven Van Elshocht, Doug Anberg, David Owen, Richard van Haren

Proceedings Volume 10145, 101452L (2017) https://doi.org/10.1117/12.2257475

KEYWORDS: Lithographic process control, Forward error correction, Distortion, Lithographic metrology, Semiconducting wafers, Overlay metrology, Scanners, Metrology, Thin films, Process control, Silicon films, Semiconductor manufacturing

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Proceedings Article | 28 March 2016 Paper

Toward sub-20nm pitch Fin patterning and integration with DSA

Safak Sayan, Taisir Marzook, BT Chan, Nadia Vandenbroeck, Arjun Singh, David Laidler, Efrain Sanchez, Philippe Leray, Paulina R. Delgadillo, Roel Gronheid, Geert Vandenberghe, William Clark, Aurelie Juncker

Proceedings Volume 9779, 97790R (2016) https://doi.org/10.1117/12.2220120

KEYWORDS: Directed self assembly, Optical lithography, Optical alignment, Semiconducting wafers, Etching, Photomasks, Image processing, Scanners, Wafer-level optics

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Proceedings Article | 12 April 2013 Paper

Impact of process decisions and alignment strategy on overlay for the 14nm node

David Laidler, Koen D’havé, Philippe Leray, Jan Hermans, Juergen Boemmels, Shaunee Cheng, Huixiong Dai, Yongmei Chen, Bencherki Mebarki, Chris Ngai

Proceedings Volume 8683, 868306 (2013) https://doi.org/10.1117/12.2011968

KEYWORDS: Optical alignment, Etching, Back end of line, Metals, Copper, Double patterning technology, Chemical mechanical planarization, Scanners, Neodymium, Optical lithography

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Proceedings Article | 1 April 2013 Paper

Towards manufacturing a 10nm node device with complementary EUV lithography

Jan Hermans, Huixiong Dai, Ardavan Niroomand, David Laidler, Ming Mao, Yongmei Chen, Philippe Leray, Chris Ngai, Shaunee Cheng

Proceedings Volume 8679, 86791K (2013) https://doi.org/10.1117/12.2012136

KEYWORDS: Semiconducting wafers, Extreme ultraviolet lithography, Etching, Extreme ultraviolet, Reticles, Critical dimension metrology, Optical lithography, Line width roughness, Manufacturing, Overlay metrology

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Proceedings Article | 4 April 2012 Paper

Overlay accuracy with respect to device scaling

Philippe Leray, David Laidler, Shaunee Cheng

Proceedings Volume 8324, 832409 (2012) https://doi.org/10.1117/12.918017

KEYWORDS: Overlay metrology, Scanners, Etching, Optical design, Silicon, Metrology, Semiconducting wafers, Reticles, Diffraction, Neodymium

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Proceedings Article | 14 March 2012 Paper

Progress in EUV lithography towards manufacturing from an exposure tool perspective

Jan Hermans, David Laidler, Philippe Foubert, Koen D'havé, Shaunee Cheng, Mircea Dusa, Eric Hendrickx

Proceedings Volume 8322, 832202 (2012) https://doi.org/10.1117/12.917616

KEYWORDS: Semiconducting wafers, Reticles, Optical alignment, Scanners, Extreme ultraviolet lithography, Overlay metrology, Critical dimension metrology, Extreme ultraviolet, Silicon, Manufacturing

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Proceedings Article | 13 March 2012 Paper

Mix and match overlay optimization strategy for advanced lithography tools (193i and EUV)

David Laidler, Koen D'havé, Jan Hermans, Shaunee Cheng

Proceedings Volume 8326, 83260M (2012) https://doi.org/10.1117/12.916969

KEYWORDS: Scanners, Extreme ultraviolet lithography, Overlay metrology, Extreme ultraviolet, Semiconducting wafers, Reticles, Optical alignment, Lithography, Metrology, Silicon

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Proceedings Article | 20 April 2011 Paper

Verification and extension of the MBL technique for photo resist pattern shape measurement

Miki Isawa, Maki Tanaka, Hideyuki Kazumi, Chie Shishido, Akira Hamamatsu, Norio Hasegawa, Peter De Bisschop, David Laidler, Philippe Leray, Shaunee Cheng

Proceedings Volume 7971, 79710Z (2011) https://doi.org/10.1117/12.878960

KEYWORDS: Cadmium, Critical dimension metrology, Photoresist materials, Atomic force microscopy, Metrology, Scanning electron microscopy, Finite element methods, Terbium, Semiconducting wafers, Double patterning technology

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Proceedings Article | 20 April 2011 Paper

Diffraction based overlay re-assessed

Philippe Leray, David Laidler, Koen D'havé, Shaunee Cheng

Proceedings Volume 7971, 797114 (2011) https://doi.org/10.1117/12.882353

KEYWORDS: Overlay metrology, Calibration, Metrology, Semiconducting wafers, Process control, Etching, Silicon, Scanners, Metals, Diffraction

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Proceedings Article | 8 April 2011 Paper

Overlay progress in EUV lithography towards adoption for manufacturing

Jan Hermans, David Laidler, Charles Pigneret, Andre van Dijk, Oleg Voznyi, Mircea Dusa, Eric Hendrickx

Proceedings Volume 7969, 79691M (2011) https://doi.org/10.1117/12.881088

KEYWORDS: Semiconducting wafers, Optical alignment, Reticles, Overlay metrology, Extreme ultraviolet lithography, Silicon, Scanners, Extreme ultraviolet, Coating, Thermal effects

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Proceedings Article | 2 April 2010 Paper

Achieving optimum diffraction based overlay performance

Philippe Leray, David Laidler, Shaunee Cheng, Martyn Coogans, Andreas Fuchs, Mariya Ponomarenko, Maurits van der Schaar, Peter Vanoppen

Proceedings Volume 7638, 76382B (2010) https://doi.org/10.1117/12.848524

KEYWORDS: Chemical mechanical planarization, Overlay metrology, Metrology, Diffraction, Semiconducting wafers, Polarization, Silicon, Diffraction gratings, Oxides, Scatterometry

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Proceedings Article | 2 April 2010 Paper

A single metrology tool solution for complete exposure tool setup

David Laidler, Koen D'havé, Anne-Laure Charley, Philippe Leray, Shaunee Cheng, Mircea Dusa, Peter Vanoppen, Paul Hinnen

Proceedings Volume 7638, 763809 (2010) https://doi.org/10.1117/12.848388

KEYWORDS: Semiconducting wafers, Scanners, Overlay metrology, Metrology, Calibration, Control systems, Scatterometry, Process control, Reticles, Diffraction

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Proceedings Article | 2 April 2010 Paper

Scatterometry metrology validation with respect to process control

Philippe Leray, Shaunee Cheng, David Laidler, Koen D'havé, Anne-Laure Charley

Proceedings Volume 7638, 76380X (2010) https://doi.org/10.1117/12.848535

KEYWORDS: Scatterometry, Process control, Critical dimension metrology, Lithography, Metrology, Semiconducting wafers, Scanning electron microscopy, Scanners, Scatter measurement, Reflectometry

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Proceedings Article | 2 April 2010 Paper

Focus and dose deconvolution technique for improved CD control of immersion clusters

Anne-Laure Charley, Koen D'havé, Philippe Leray, David Laidler, Shaunee Cheng, Mircea Dusa, Paul Hinnen, Peter Vanoppen

Proceedings Volume 7638, 763808 (2010) https://doi.org/10.1117/12.848444

KEYWORDS: Semiconducting wafers, Critical dimension metrology, Scanners, Data modeling, Scatterometry, Metrology, Lithography, Finite element methods, Reticles, Scatter measurement

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Proceedings Article | 23 March 2010 Paper

Performance of the ASML EUV Alpha Demo Tool

Jan Hermans, Eric Hendrickx, David Laidler, Christiane Jehoul, Dieter Van Den Heuvel, Anne-Marie Goethals

Proceedings Volume 7636, 76361L (2010) https://doi.org/10.1117/12.848210

KEYWORDS: Semiconducting wafers, Reticles, Critical dimension metrology, Extreme ultraviolet, Silicon, Lithography, Extreme ultraviolet lithography, Overlay metrology, Photoresist processing, Scanners

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The 22nm technology node is the target for insertion of Extreme Ultra-Violet (EUV) lithography into pre-production. To prepare this insertion, the issues that arise with the use of an EUV lithographic scanner in a pre-production environment need to be addressed. To gain better understanding of the issues that come with an EUV lithographic scanner, the Alpha Demo Tool (ADT) from ASML was installed at IMEC and is now in use since mid of 2008. In July 2009, the source was upgraded to a 170W/2π source to allow for higher uptime and wafer output by means of the semi-automatic tin refill. Also a new advanced resist, the SEVR-59 resist was introduced after the installation of the 170W/2π source to allow printing of 32nm Lines-Spaces (LS). After these changes, the ADT has been monitored closely with respect to the imaging performance. In this paper, we report on both the CD fingerprint analysis and the exposure tool stability. For 32nm dense LS, the ADT shows a wafer CD Uniformity (CDU) of 2.5nm 3σ, without any corrections for process or reticle. As for 40nm LS, the wafer CDU is correlated to different factors that are known to influence the CD fingerprint from traditional lithography: reticle CD error, slit intensity uniformity, focal plane deviation but also EUV specific reticle shadowing. The ADT shows excellent wafer-to-wafer stability (<0.5nm CD range in a 5-wafer lot) and the average CD as a function of exposure sequence is stable (<0.5nm 3σ in a 5-wafer lot). The ADT shows good CD stability over 5 months of operation with the 170W/2π source, both intrafield and across wafer. There is a 5nm difference in overlay performance (measured or after corrections) between the ADT and the XT:1900Gi production tool (using the same etched silicon wafers as a reference). Below 32nm, the ADT shows good wafer CDU for 30nm dense LS (60nm pitch). First 27nm dense line CDU data are achieved (54nm pitch). The results indicate that the ADT can be used effectively for EUV process development before installation of the pre-production tool, the ASML NXE:3100 at IMEC.

Proceedings Article | 24 March 2009 Paper

Track optimization and control for 32nm node double patterning and beyond

David Laidler, Craig Rosslee, Koen D'havé, Philippe Leray, Len Tedeschi

Proceedings Volume 7272, 727236 (2009) https://doi.org/10.1117/12.814849

KEYWORDS: Etching, Semiconducting wafers, Double patterning technology, Calibration, Metrology, Photoresist processing, Scanners, Polarization, Zone plates, Critical dimension metrology

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Proceedings Article | 24 March 2009 Paper

A practical application of multiple parameters profile characterization (MPPC) using CD-SEM on production wafers using Hyper-NA lithography

T. Ishimoto, K. Sekiguchi, N. Hasegawa, K. Watanabe, D. Laidler, S. Cheng

Proceedings Volume 7272, 72722E (2009) https://doi.org/10.1117/12.814164

KEYWORDS: Lithography, Critical dimension metrology, Semiconducting wafers, Process control, Finite element methods, Scanning electron microscopy, Printing, Photoresist processing, Temperature metrology, Immersion lithography

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Proceedings Article | 23 March 2009 Paper

Overlay metrology for double patterning processes

Philippe Leray, Shaunee Cheng, David Laidler, Daniel Kandel, Mike Adel, Berta Dinu, Marco Polli, Mauro Vasconi, Bartlomiej Salski

Proceedings Volume 7272, 72720G (2009) https://doi.org/10.1117/12.814182

KEYWORDS: Overlay metrology, Double patterning technology, Semiconducting wafers, Diffraction, Scanners, Calibration, Metrology, Diffraction gratings, Spectroscopy, Polarizers

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The double patterning (DPT) process is foreseen by the industry to be the main solution for the 32 nm technology node and even beyond. Meanwhile process compatibility has to be maintained and the performance of overlay metrology has to improve. To achieve this for Image Based Overlay (IBO), usually the optics of overlay tools are improved. It was also demonstrated that these requirements are achievable with a Diffraction Based Overlay (DBO) technique named SCOL^TM [1]. In addition, we believe that overlay measurements with respect to a reference grid are required to achieve the required overlay control [2]. This induces at least a three-fold increase in the number of measurements (2 for double patterned layers to the reference grid and 1 between the double patterned layers). The requirements of process compatibility, enhanced performance and large number of measurements make the choice of overlay metrology for DPT very challenging. In this work we use different flavors of the standard overlay metrology technique (IBO) as well as the new technique (SCOL) to address these three requirements. The compatibility of the corresponding overlay targets with double patterning processes (Litho-Etch-Litho-Etch (LELE); Litho-Freeze-Litho-Etch (LFLE), Spacer defined) is tested. The process impact on different target types is discussed (CD bias LELE, Contrast for LFLE). We compare the standard imaging overlay metrology with non-standard imaging techniques dedicated to double patterning processes (multilayer imaging targets allowing one overlay target instead of three, very small imaging targets). In addition to standard designs already discussed [1], we investigate SCOL target designs specific to double patterning processes. The feedback to the scanner is determined using the different techniques. The final overlay results obtained are compared accordingly. We conclude with the pros and cons of each technique and suggest the optimal metrology strategy for overlay control in double patterning processes.

Proceedings Article | 23 March 2009 Paper

Immersion specific error contribution to overlay control

Koen D'havé, David Laidler, Shaunee Cheng

Proceedings Volume 7272, 72720D (2009) https://doi.org/10.1117/12.814923

KEYWORDS: Semiconducting wafers, Data modeling, Overlay metrology, Scanners, Error analysis, Immersion lithography, Double patterning technology, Motion models, Process modeling, Reticles

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Proceedings Article | 23 March 2009 Paper

Performance verification of resist loss measurement method using top-view CD-SEM images for hyper-NA lithography

Mayuka Osaki, Maki Tanaka, Chie Shishido, Shaunee Cheng, David Laidler, Monique Ercken, Efrain Altamirano

Proceedings Volume 7272, 727211 (2009) https://doi.org/10.1117/12.813472

KEYWORDS: Etching, Semiconducting wafers, Surface roughness, Finite element methods, Scanning electron microscopy, Lithography, Atomic force microscopy, Critical dimension metrology, Atomic force microscope, Photoresist processing

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Proceedings Article | 4 December 2008 Paper

Cluster optimization to improve CD control as an enabler for double patterning

Len Tedeschi, Craig Rosslee, David Laidler, Philippe Leray, Koen D'havé

Proceedings Volume 7140, 714023 (2008) https://doi.org/10.1117/12.805239

KEYWORDS: Semiconducting wafers, Etching, Critical dimension metrology, Double patterning technology, Error analysis, Scanners, Metrology, Polarization, Photoresist processing, Lithographic illumination

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Proceedings Article | 16 April 2008 Paper

Further study on the verification of CD-SEM based monitoring for hyper NA lithography

T. Ishimoto, M. Osaki, K. Sekiguchi, N. Hasegawa, K. Watanabe, D. Laidler, S. Cheng

Proceedings Volume 6922, 69222O (2008) https://doi.org/10.1117/12.771894

KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Signal detection, Lithography, Signal attenuation, Semiconducting wafers, Process control, 3D metrology, Finite element methods, Metrology

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Proceedings Article | 16 April 2008 Paper

Advanced CD-SEM metrology to improve total process control performance for hyper-NA lithography

Mayuka Osaki, Maki Tanaka, Chie Shishido, Toru Ishimoto, Norio Hasegawa, Kohei Sekiguchi, Kenji Watanabe, Shaunee Cheng, David Laidler, Monique Ercken, Efrain Altamirano

Proceedings Volume 6922, 69221B (2008) https://doi.org/10.1117/12.771886

KEYWORDS: Critical dimension metrology, Etching, Photoresist processing, Lithography, Scanning electron microscopy, Semiconducting wafers, Finite element methods, Signal attenuation, Process control, Metrology

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Proceedings Article | 24 March 2008 Paper

Sources of overlay error in double patterning integration schemes

David Laidler, Philippe Leray, Koen D’havé, Shaunee Cheng

Proceedings Volume 6922, 69221E (2008) https://doi.org/10.1117/12.773575

KEYWORDS: Semiconducting wafers, Optical alignment, Overlay metrology, Double patterning technology, Metrology, Etching, Manufacturing, Oxides, Photomasks, Immersion lithography

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Proceedings Article | 5 April 2007 Paper

Advanced process control for hyper-NA lithography based on CD-SEM measurement

T. Ishimoto, K. Sekiguchi, N. Hasegawa, T. Maeda, K. Watanabe, G. Storms, D. Laidler, S. Cheng

Proceedings Volume 6518, 65182P (2007) https://doi.org/10.1117/12.710814

KEYWORDS: Lithography, Critical dimension metrology, Process control, Precision measurement, Semiconducting wafers, Scanning electron microscopy, Electroluminescence, Metrology, Finite element methods, Resolution enhancement technologies

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With the recent introduction of immersion lithography, optical systems with numerical aperture (NA) reaching 1.0 or larger can be realized. Various Resolution Enhancement Techniques (RET) such as various phase shift mask approaches have been used to push even further the resolution limit by reducing k₁ scaling factor, including Double Patterning Technology. However, with the improved resolution by Hyper-NA and Low-k₁, lithographers face the problem of decreasing Depth of Focus and in turn reduced process latitude. Throughout the industry, Process Window has been widely used as an analytical tool to evaluate process latitude for a given design feature size; therefore, the ability to accurately and efficiently derive a Process Window within which a process can run on target and in control is fundamental to Low-k₁ lithography. Accuracy of Process Window derivation is based on the ability to accurately measure and model the physical dimension of the design feature and how it changes in response to changes in process parameters. In the case of lithography, the Process Window of a desired critical dimension target is bounded by changes in exposure energy and defocus. To be able to accurately measure the physical dimension of the design feature remains a big challenge for metrologists especially in the presence of other process noise. In this work, it is shown that the precision of PW measurement can be enhanced by using CD-ACD (Average CD) function to measure a FEM (Focus-Exposure matrix) wafer. ACD is a function, which simultaneously measures several points, thus providing higher precision measurement in comparison to the conventional single point measurement. As seen in this work, by using ACD measurements to derive the Process Window, there is a significantly improvement in the stability of the derived Process Window. Also reported is the MPPC (Multiple Parameters Profile Characterization) ^*1), a function which provides the ability to extract pattern shape information from a measured e-beam signal. This function together with the ACD function enables PW measurement with high precision, which also takes into account the actual pattern shape. PW derived from conventionally measured data was compared with PW derived from ACD and MPPC measurement and we were able to demonstrate an improvement of more than 30% in precision of PW determination.

Proceedings Article | 4 April 2007 Paper

Comparison of back side chrome focus monitor to focus self-metrology of an immersion scanner

Koen D'havé, Takahiro Machida, David Laidler, Shaunee Cheng

Proceedings Volume 6518, 651805 (2007) https://doi.org/10.1117/12.714255

KEYWORDS: Semiconducting wafers, Scanners, Monochromatic aberrations, Calibration, Metrology, Optical alignment, Reticles, Wafer testing, Immersion lithography, Overlay metrology

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Proceedings Article | 15 March 2006 Paper

Immersion effects on lithography system performance

Seiji Nagahara, Ivan Pollentier, Takahiro Machida, Sean O'Brien, Eric Jacobs, Charles Schaap, Philippe Leray, Greet Storms, Kathleen Nafus, David Laidler, Shaunee Cheng

Proceedings Volume 6154, 61540U (2006) https://doi.org/10.1117/12.659620

KEYWORDS: Semiconducting wafers, Thin film coatings, Scanners, Temperature metrology, Reticles, Immersion lithography, Scatterometry, Lithography, Overlay metrology, Scatter measurement

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The immersion effects on lithography-system performance have been investigated using a ASML TWINSCAN XT:1250Di immersion-ArF scanner (NA=0.85) and Tokyo Electron CLEAN TRACK ACT12 at IMEC. Effects of immersion-induced-temperature change and effects of material-top surface are discussed in this paper. The wafer-stage temperature is measured during the leveling-verification tests and compared with the observed residual-focus-error change. The results indicate that stage-temperature change under an immersion environment can induce a focus change. In this paper, it was proved that the improved-temperature-control stage is effective to mitigate the immersion-specific focus change. The immersion effect on overlay is also investigated as a function of material top surface. It was demonstrated that the effect of material-receding-contact angles on the grid-residual errors (non-correctable errors) is small in the latest-immersion-hardware configuration of the scanner. However, there was a tendency that material with a smaller-receding-contact angle has a larger-wafer scaling although it is a correctable parameter. This can be caused by the first-layer wafer shrinkage due to more water evaporation on the more-hydrophilic surface. The immersion effect on scanner-dynamic performance is then investigated by changing the material-top surface and the scan speed of the scanner. It was turned out that the scan synchronization is not much affected by differences of material receding-contact-angles for the new configuration of the scanner. Moving-standard deviation of the synchronization error in scanning direction (y-direction) is slightly more affected by increased scanning speed, although it stays within specification even at a maximum scan speed of 500 mm/sec. Finally the immersion effects on resist-profile uniformity are examined. It was found that lower-leaching-film stacks (with a top coat or a lower leaching resist) seem to mitigate the variation of resist-profile uniformity.

Proceedings Article | 10 May 2005 Paper

Identifying sources of overlay error in FinFET technology

David Laidler

Proceedings Volume 5752, (2005) https://doi.org/10.1117/12.598746

KEYWORDS: Semiconducting wafers, Optical alignment, Error analysis, Overlay metrology, Silicon, Transistors, Materials processing, Oxides, Oxidation

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Proceedings Article | 29 April 2004 Paper

In-line lithography cluster monitoring and control using integrated scatterometry

Ivan Pollentier, Shaunee Cheng, Bart Baudemprez, David Laidler, Youri van Dommelen, Rene Carpaij, Jackie Yu, Junichi Uchida, Anita Viswanathan, Doris Chin, Kelly Barry, Nickhil Jakatdar

Proceedings Volume 5378, (2004) https://doi.org/10.1117/12.537384

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Lithography, Metrology, Scatterometry, Process control, 193nm lithography, Control systems, Finite element methods, Time metrology

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Proceedings Article | 1 July 2003 Paper

Knowledge-based APC methodology for overlay control

David Laidler, Philippe Leray, David Crow, Keith Roberts

Proceedings Volume 5044, (2003) https://doi.org/10.1117/12.485308

KEYWORDS: Control systems, Semiconducting wafers, Overlay metrology, Optical alignment, Error analysis, Manufacturing, Data modeling, Process control, Metrology, Silicon

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Proceedings Article | 2 June 2003 Paper

Characterization of overlay mark fidelity

Mike Adel, Mark Ghinovker, Jorge Poplawski, Elyakim Kassel, Pavel Izikson, Ivan Pollentier, Philippe Leray, David Laidler

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483430

KEYWORDS: Overlay metrology, Semiconducting wafers, Reticles, Chemical mechanical planarization, Statistical analysis, Error analysis, Silicon, Manufacturing, Optical lithography, Metrology

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In this publication we introduce a new metric for process robustness of overlay metrology in microelectronic manufacturing. By straightforward statistical analysis of overlay metrology measurements on an array of adjacent, nominally identical overlay targets the Overlay Mark Fidelity (OMF) can be estimated. We present the results of such measurements and analysis on various marks, which were patterned using a DUV scanner. The same reticle set was used to pattern wafers on different process layers and process conditions. By appropriate statistical analysis, the breakdown of the total OMF into a reticle-induced OMF component and a process induced OMF component was facilitated. We compare the OMF of traditional box-in-box overlay marks with that of new gratingbased overlay marks and show that in all cases the grating marks are superior. The reticle related OMF showed an improvement of 30 % when using the new grating-based overlay mark. Furthermore, in a series of wafers run through an STI-process with different Chemical Mechanical Polish (CMP) times, the random component of the OMF of the new grating-based overlay mark was observed to be 40% lower and 50% less sensitive to process variation compared with Box in Box marks. These two observations are interpreted as improved process robustness of the grating mark over box in box, specifically in terms of reduced site by site variations and reduced wafer to wafer variations as process conditions change over time. Overlay Mark Fidelity, as defined in this publication, is a source of overlay metrology uncertainty, which is statistically independent of the standard error contributors, i.e. precision, TIS variability, and tool to tool matching. Current overlay metrology budgeting practices do not take this into consideration when calculating total measurement uncertainty (TMU). It is proposed that this be reconsidered, given the tightness of overlay and overlay metrology budgets at the 70 nm design rule node and below.

Proceedings Article | 2 June 2003 Paper

Comparison of pattern placement errors as measured using traditional overlay targets and design rule structures

Philippe Leray, David Laidler, Ivan Pollentier

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.482817

KEYWORDS: Personal protective equipment, Overlay metrology, Semiconducting wafers, Metrology, Reticles, Scanning electron microscopy, Structural design, Wafer-level optics, Data modeling, Reliability

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Proceedings Article | 16 July 2002 Paper

Advances in process overlay: ATHENA alignment system performance on critical process layers

David Laidler, Henry Megens, Sanjay Lalbahadoersing, Richard van Haren, Frank Bornebroek

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473478

KEYWORDS: Optical alignment, Chemical mechanical planarization, Semiconducting wafers, Oxides, Polishing, Metals, Signal processing, Overlay metrology, Copper, Dielectrics

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Proceedings Article | 16 July 2002 Paper

Comparison of ATHENA and TTL alignment capability in product wafers

Juliann Opitz, David Laidler

Proceedings Volume 4689, (2002) https://doi.org/10.1117/12.473411

KEYWORDS: Optical alignment, Data transmission, Semiconducting wafers, Chemical mechanical planarization, Overlay metrology, Polishing, Diffraction, Scanning probe microscopy, Manufacturing, Thin films

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Proceedings Article | 22 August 2001 Paper

Advances in process overlay

Paul Hinnen, Henry Megens, Maurits van der Schaar, Richard van Haren, Evert Mos, Sanjay Lalbahadoersing, Frank Bornebroek, David Laidler

Proceedings Volume 4344, (2001) https://doi.org/10.1117/12.436734

KEYWORDS: Semiconducting wafers, Optical alignment, Copper, Overlay metrology, Metals, Metrology, Silicon, Aluminum, Chemical mechanical planarization, Polishing

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Showing 5 of 35 publications

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