As the industry accelerates the reduction in sub-wavelength device feature sizes, it is necessary that the traditional barriers between design, mask data preparation (MDP), and the lithography process be broken down or eliminated. These processes, which now possess increased levels of complexity and interconnectivity, can no longer work independently but must be linked and all applicable information about the processes propagated upstream.
Options associated with phase shift masks, optical proximity correction, increasing constraints for the minimum defect size requirements, improving yield and throughput, etc. have been key to the increased demands placed on the photomask manufacturers. Knowledge of the lithographic performance of a selected option prior to mask build is key to reducing mask cost, improving turn around time and staying on the aggressive path established by the mask user.
Integrating CD and lithographic process window analysis with MDP provides a convenient means of helping the mask makers to predict the performance of a mask within the wafer fab. This paper will discuss the integration of CD and lithographic process window analysis tools with CATS mask data preparation software. The benefits of implementing this methodology will be explored and illustrated with data.
The impact of photo mask manufacturing errors in the photolithography process and subsequently on the final device and test circuit (ring oscillator) performance are investigated. A statistical Monte Carlo process generates a population of normally distributed simulated photo mask errors during the reticle manufacturing process. Further steps predict how these photo mask errors impact printed poly gate patterns under different lithography conditions. Sensitivity analysis performed with the Sequoia Device Designer software tool identified the metal oxide semiconductor field effect transistor (MOSFET) channel length (Lpoly) as the most sensitive MOSFET parameter and an estimate of the distribution of device performance for realistic photo mask errors is made.
This is an extension of our previous work where we discussed basic assumptions of device oriented process verification. Here, we propose an integrated procedure to verify the design of active devices and interconnections. It entails extraction of device, contact, and interconnect electrical performance based on optical simulation of layout geometries, including proximity correction features, combined with critical dimension (CD) variation and misalignment. A critical analysis, proposed in this work, made it possible to focus the simulation on the selected process corner options. We integrated multi-level optical and device simulation to verify dense layouts for deep sub- wavelength design rules in a six-transistor advanced memory cell.
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