With moving from one process node to another, process effect corrections are becoming a very challenging task. High
quality models, long run times and extensively large computer resources are needed to perform a typical modern process
effect correction procedure. Since the patterns that form IC layouts are highly repetitive, all the modern process
correction algorithms try to take advantage of this fact to decrease processing time and computer resources requirements.
However, currently used high accuracy process effect correction algorithms are becoming less and less advantageous
because of the increasing relative non-locality of the process effects. In this paper, we investigate the feasibility of a
simpler approach called "cell-wise corrections". We propose a recipe for the cell-wise process effect correction and analyze its accuracy using a 65 nm test layout. The recipe is fully automated and implemented using a commercially
available OPC tool. The analysis reveals good accuracy and feasibility of our approach.
Trends in the design feature shrinking that outrun the progress in the lithography technologies require critical efforts in
the layout, process, and model development. Printing a layout is no longer a problem only for the lithographers; it has
penetrated into the layout stage as well. Layout patterns are getting more aggressive, raising serious printability
concerns. This requires very accurate models to analyze the manufacturability issues. This also often requires
simultaneous analysis and optimization of both layout and the process. Most advanced layout patterns are extremely
hard to manufacture and consequently run into the risk of re-spins. Therefore, an early pre-tapeout analysis and
troubleshooting of various layout, process, and RET issues has become a very important task. Our paper gives examples
of how these and other related issues can be addressed using a commercially available Design-for-Yield integrated