In order to optimize the time to market of the newest technology nodes and maximize their profitability, advanced semiconductor manufacturers need to adapt their yield enhancement strategies to their current development stage. During very early development, gross Defectivity at some critical process steps often makes it impractical to use broadband plasma or laser scanning micro-defect patterned wafer inspection techniques: such sensitive defect inspections capture a large number of defects, producing wafer defect maps so heavily populated that even wafer level signature are difficult to visualize.
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