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In this paper, we will introduce experimental results of wafer topography effect using various test patterns and propose a simple method that could effectively reduce wafer topography effect.
We report on the influence of several AIMS parameters on the defect analysis including repair point. Under various illumination conditions with different patterns, it showed the significant correlation in defect analysis results. It is able to analyze defect under certain error budget based on the management specification required for each layer. In addition, it provided us with one of the clues in the analysis of wafer repeating defect. Finally we will present 'optimal specification' for defect management with common AIMS recipe and suggest advanced mask process flow.
In this study, we investigated new method to measure MoSi pattern CD before Cr strip process to eliminate the CD gap between MoSi pattern and Cr/MoSi pattern. To eliminate the CD gap, we attempt three solutions – 1) Optimize etch process to perform perfect Cr/MoSi pattern profile without the CD gap, 2) Improve CD measurement accuracy by developing new SEM measuring mechanism, 3) Develop of new process to modify Cr/MoSi pattern profile to be measured without the CD gap. It was found that the CD gap can be eliminated and MoSi pattern CD can be measured perfectly. Finally, MoSi pattern CD control was improved because of CD gap elimination.
Generally, film deposition process is widely used for repairing clear defects. However, the deposited film has weak cleaning durability, so it is easily removed by accumulated cleaning process. Although the deposited film is strongly attached on MoSiN(or Qz) film, the adhesive strength between deposited Cr film and MoSiN(or Qz) film becomes weaker and weaker by the accumulated energy when masks are exposed in a scanner tool due to the different coefficient of thermal expansion of each materials. Therefore, whenever a re-pellicle process is needed to a mask, all deposited repair points have to be confirmed whether those deposition film are damaged or not. And if a deposition point is damaged, repair process is needed again. This process causes longer and more complex process.
In this paper, the basic theory and the principle are introduced to recover clear defects by using nanomachining tool, and the evaluated results are reviewed at dense line (L/S) patterns and contact hole (C/H) patterns. Also, the results using a nanomachining were compared with those using an e-beam repair tool, including the cleaning durability evaluated by the accumulated cleaning process. Besides, we discuss the phase shift issue and the solution about the image placement error caused by phase error.
However, measuring mask registration performance accurately on tilted lines was a challenge. KLA Tencor applied the model-based algorithm to enable the accurate registration measurement of tilted lines on the Poly layer as well as the mask-to-mask overlay to the adjacent contact layers. The metrology solution is discussed and measurement results are provided.
In this paper, we introduce a new HSF method that is able to make OPC TAT shorter than the common HSF method. The new HSF method consists of two concepts. The first one is that OPC target point is controlled to fix HSP. Here, the target point should be moved to optimum position at where the edge placement error (EPE) can be 0 at critical points. Many parameters such as a model accuracy or an OPC recipe become the cause of larger EPE. The second one includes controlling of model offset error through target point adjustment. Figure 1 shows the case EPE is not 0. It means that the simulation contour was not targeted well after OPC process. On the other hand, Figure 2 shows the target point is moved -2.5nm by using target point control function. As a result, simulation contour is matched to the original layout. This function can be powerfully adapted to OPC procedure of memory and logic devices.
The influence of the measurement devices (wireless and wired sensor arrays) used to optimize the hotplate, on the performance of the Post Exposure Bake (PEB) process is discussed in [1,2]. A concept of utilizing two wired sensor arrays, with wire connections attached in opposite locations on the sensor array surface, called “Mirror Bake” is introduced. Based on the individual hotplate optimization for each of those two sensor arrays, a combined bake recipe for the multi-zone hotplate is calculated. This method eliminates the systematic temperature non-uniformity introduced by the sensor array hardware, when optimizing the recipes with only one sensor array.
In this paper the “mirror bake” concept is validated by comparing the CD uniformity data of masks manufactured with a PEB process, optimized using a single standard sensor array vs. the “mirror bake” concept. The “mirror bake” concept achieved a CD uniformity improvement of up to 30% (CD range). During this work additional hardware influences from the sensor arrays were identified.
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