An optical design of EUV attenuated PSM is proposed for contact-hole imaging. LCDU depends on MEEF as well as NILS. If co-optimization of MEEF and NILS is carried out, EUV PSM performs better when the PSM reflectance is higher. In order to make a high-reflectance PSM, the shifter materials should be as transparent as possible. Since the shifter’s thickness variation throughout the mask can cause phase and reflectance variation and thus global CD variation, its thickness should be set where phase and reflectance are least sensitive to such thickness variation. In short, the shifter’s thickness should be determined to maximize PSM performance while ensuring lithography process robustness. Applying PSM so designed leads to a dramatically lower dose-to-size while maintaining LCDU at the same level. Proposed PSM is manufacturable and effective in increasing throughput of EUV lithography.
The next-generation high-NA EUV scanner is being developed to enable patterning beyond the 3-nm technology node. Design and development of the scanner are based on rigorous litho-simulations. It is important to verify key imaging simulation findings by means of aerial image experiments with representative high-NA scanner characteristics. The first ASML-SHARP joint experiment was done with lines and spaces with pitches down to 16 nm wafer scale (1x). The experimental results confirmed the key litho-simulation findings: central obscuration’s impact on high-NA imaging and mitigations of obscuration’s impact using flex illuminations.
The mask is a known contributor to intra-field fingerprints at the wafer level. Traditionally, a 3σ distribution of critical dimensions (CDs) on mask was considered sufficient to characterize the contribution to the CD distribution at wafer level. Recent studies report wafer local CD distributions characterized for statistics beyond 3σ1. Mask has been shown to contribute to wafer local CD distribution also which is typically quantified as Local CD Uniformity (LCDU), a 3σ metric2. Additionally, the local placement distribution on wafer could be a contributor to Edge Placement Error (EPE)3. Consequently, it is imperative to understand, characterize and ultimately control the mask contributions to local CD and placement distribution at wafer level. This work is an investigation of local CD and placement distribution on an EUV mask and its impact on distributions at wafer level.