With decreasing the design node, there are some candidates for the optical lithography technology. Double Exposure
Technology (DET) is the one of the solution to extend the resolution limit down to k1 less than 0.25 for the next
generation devices. To accomplish DET, photomask MTT, CD uniformity, and the overlay between the layers for the
dual exposure are important as the photomask process aspect.
MTT and CD uniformity have been frequently discussed for Single Exposure Technology (SET), but the overlay and
the registration have not been discussed yet with the view of DET. In this work, the feasibility of mask fabrication,
especially the overlay and the registration for DET are analyzed. The current mask limit of DET is discussed
considering MTT, uniformity, and overlay.
As k1 factor approaches the theoretical limit, optical proximity correction (OPC) treatments necessary to maintain dimensional tolerances involve increasingly complex correction shapes. This translates to more detailed, or larger mask pattern databases. Moreover, development of exposure tools lags behind the shrinkage of device. This may result in dwindling of process margin in lighographic process despite using all possible resolution enhancement techniques (RETs). Although model-based OPC may lose its effectiveness in case of narrower photolithographic process margin, model-based OPC is recognized as a robust tool to cope with the diversity of layout. By the way, in case of narrower photolithographic process margin, model-based OPC lose its effectiveness. To enhance the usefulness of the OPC, we need to overcome many obstacles. It is supposed that the original layout be designed friendly to lithography to enhance the process margin using aggressive RETs, and is amended by model-based OPC to suppress the proximity effect. But, some constraints are found during an OPC procedure. Ultimately, unless the original lithgraphy friendly layout (LFL) is corrected in terms of pitches and shapes, the lithography process is out of process window as well as makes pattern fidelity poor. This paper emphasizes that the application of model-based OPC requires a particular and unique layout configuration to preserve the process margin in the low k1 process.
The on-chip variation (OCV) should be critically controlled to obtain the high speed performance in logic devices. The variation from proximity dominantly contributes to OCV. This proximity effect can be compensated by applying well-treated optical proximity correction (OPC). Therefore, the accuracy of OPC is needed, and methods to enhance its result have to be devised. The optical proximity behaviors are severely varied according to the material and optical conditions. In point of material, the proximity property is affected by species of photo-resist (PR) and change of post exposure bake (PEB) conditions. 3σ values of proximity variation are changed from 9.3 nm to 15.2 nm according to PR species. Also, proximity variations change from 16.2 nm to 13.8 nm is observed according to PEB condition. Proximity variations changes of 11.6 nm and 15.2 nm are measured by changing the illumination condition. In order not to seriously deteriorate OPC, these factors should be fixed after the OPC rules are extracted. Proximity variations of 11.4 nm, 13.9 nm and 15.2 nm are observed for the mask mean-to-targets (MTT) of 0 nm, 2nm, and 4nm, respectively. The decrease the OPC grid size enhances the correction resolution and the OCV is reduced. The selective bias rule is generated by model using grid size of 1 nm and 0.5 nm. For the nominal CD of 87 nm, proximity variations are measured to be 14.6 nm and 11.4 nm for 1 nm and 0.5 nm grid sizes, respectively. The enhancement amount of proximity variations are 9.2 nm corresponding to 39% improvement. The CD uniformity improvement for adopting the small grid size is confirmed by measuring the CD uniformity on real SRAM pattern. CD uniformities are measured 11nm and 9.1nm for grid size of 1 nm and 0.5 nm, respectively. 22% improvement of the CD uniformity is achieved.
The introduction of ArF lithography technology is needed for on-chip linewidth variation(OCV) control less than 10nm in 90nm logic transistor development. Since conventional KrF lithography increased the burdens of mask fabrication and photo process due to excessive optical proximity correction(OPC), ArF lithography is more required to improve pattern feasibility in terms of line edge roughness(LER), corner rounding and contact overlapping margin than before. In this paper, we investigated two major components of OCV, that is, proximity and uniformity using ArF lithography. For a tighter CD control, the proximity can be corrected by hybrid OPC method, which is a combination of rule-based and model-based OPC. The uniformity can be effectively improved by several methods such as lithography-friendly layout formation, optimal substrate condition, decrease in MEEF and tuning of the resist process. In conclusion, by using ArF lithography we could obtain the satisfactory OCV control less than 10nm and reasonable process latitude simultaneously for 90nm logic gate under the condition of well-controlled proximity and uniformity.