We present our approach to a low-cost, highly scalable opto-electronic integration platform based on a commercial
CMOS process. In this talk, we detail the performance of the device library elements and highlight performance trade-offs
encountered in monolithically integrating optical and electronic circuits. We describe an opto-electronic integrated
circuit (OEIC) design toolkit modeled after the standard electronic design flow, which includes automated design rule
checking (DRC) and layout-versus-schematic (LVS) checks covering all types of circuit elements. As an example of
integration, we detail the design of a multi-channel transceiver chip with 10 Gbps/channel optical data transmission
speed and report on its performance.
A CMOS circuit topology is demonstrated for the amplification of high-frequency AC currents without requiring similar DC current amplification. This technique is useful for current-domain amplification and processing of signals when low DC power consumption is necessary. Large amounts of AC gain can be achieved using this technique without requiring equivalent DC current gain, which would increase power consumption. Two amplifiers designed using this concept are discussed, one based on a standard current mirror architecture and the second using a cascode-type configuration. Measured results and analysis show the efficacy of this technique for the amplification of multi-Gb/s current-domain signals when implemented in a 0.12μm CMOS technology. Single-stage AC current gains of 12dB are achieved with unity DC current gain, while operating from supply voltages less than 1.0V. Temperature stable gain is also achieved.
High speed, efficient photodetectors are difficult to fabricate in standard silicon fabrication processes due to the long absorption length of silicon. However, high performance servers will soon require dense optical interconnects with low cost and high reliability, and this trend favors monolithic silicon receivers over hybrid counterparts. Recently, lateral PIN photodiode structures have been demonstrated in silicon CMOS technology with little or no process modifications. Optical receivers based on these detectors have achieved record performance in terms of speed and sensitivity. This paper will discuss the advantages, issues and recent advances in silicon-based photodetectors and optical receivers. This includes the fastest photodetector ever implemented in a standard bulk CMOS process, a 13.9 Gb/s lateral trench detector implemented in a modified EDRAM process, and a >15 GHz pure germanium photodiode grown directly on a silicon substrate.
A novel current-mode transimpedance amplifier (TIA) architecture is proposed for optical receivers. This new architecture, based around the use of a uniquely biased common-base current buffer stage, allows stable, DC coupled TIAs to be designed in bipolar or CMOS processes operating from extremely low supply voltages and using very low levels of power. Noise performance is comparable to that of higher power designs that operate from higher supply rails. Simulation results have been obtained for a 47GHz fT SiGe BiCMOS process and also 0.25μm CMOS.