Ms. Dyiann Chou Profile

Dyiann Chou

Technical Communications Mananger at Siemens EDA

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Publications (9)

Proceedings Article | 14 December 2009 Paper

Comparison of rule-based versus model-based decomposition technique

Pat LaCour, Aasutosh Dave, Dyiann Chou, Omar El Sewefy

Proceedings Volume 7520, 752011 (2009) https://doi.org/10.1117/12.837204

KEYWORDS: Double patterning technology, Nanoimprint lithography, Lithography, Model-based design, Optical proximity correction, Visualization, Photomasks, Optical lithography, Shape analysis, Process modeling

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Proceedings Article | 13 March 2009 Paper

The PIXBAR OPC for contact-hole pattern in sub-70-nm generation

KunYuan Chen, ChunCheng Liao, ShuHao Chen, Todd Wey, Phoeby Cheng, Pinjan Chou, Jochen Schacht, Dyiann Chou, Srividya Jayaram

Proceedings Volume 7275, 72750Z (2009) https://doi.org/10.1117/12.813985

KEYWORDS: Optical proximity correction, Semiconducting wafers, Atrial fibrillation, Photomasks, Autoregressive models, Reticles, Electroluminescence, Lithography, Model-based design, Manufacturing

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Proceedings Article | 4 December 2008 Paper

Image parameter-based scatter bar optimization

Ryan Chou, Li-Tung Hsiao, H. Y. Liao, Jack Lin, Regina Shen, Jochen Schacht, Dyiann Chou, Srividya Jayaram, Pat LaCour

Proceedings Volume 7140, 71402E (2008) https://doi.org/10.1117/12.804707

KEYWORDS: Printing, Optical proximity correction, Model-based design, Critical dimension metrology, Lithography, Optimization (mathematics), Manufacturing, SRAF, Resolution enhancement technologies, Semiconducting wafers

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Scatter Bar (SBAR) insertion is a computationally expensive operation. SBAR are usually generated rule-based. SBAR rule tables dictate the insertion of SBAR with different SBAR width dependent on the width of the printable main features and the spacing between the main features and SBAR. Optimization of the SBAR rules drives manufactures to ever more complex SBAR tables which increase the runtime. In advanced process nodes, SBAR printing issues, missing SBAR due to clean-up problems and joining SBAR of different width together remain challenging. On the other hand, pixelized inversion methods may yield optimized SBAR solutions, especially in terms of SBAR placement for contact layers, but comes at the expense of significant computational effort and increased mask writing and inspection time. Since OPC changes the spacing between SBAR and main features, an accurate and optimized SBAR solution requires OPC and SBAR optimization to run interactively. This work focuses on both line/space and contact layers To ensure fast SBAR optimization, SBAR placement and SBAR width optimization are separated. SBAR of uniform width are placed fast driven by a simple rule-based table comprising only a single SBAR width. This intermediate SBAR layer is subject into a model-based approach, which fragments the SBAR layer based on proximity with respect to the main features or other SBAR, and assigns measurement sites to each SBAR fragment. A model is used to move each SBAR fragment inward or outward so that the image cut line shows a maximum SBAR intensity closer to a predefined SBAR printing threshold. While the main features are unchanged, several iterations are applied to converge the SBAR fragments. Keeping the SBAR fragments fixed, OPC is applied to the main features. Repeating these steps allows optimization of the SBAR width and the OPC simultaneously. Site based as well as contours based verification methods are applied to ensure that the SBAR printing margin has been significantly improved. The improved SBAR printing margin allows manufactures to apply more aggressive SBAR placement rules, which, in addition to the optimized SBAR width, helps to enlarge the depth of focus, therefore, widen the common process window of the lithography process.

Proceedings Article | 24 March 2006 Paper

Toward full-chip prediction of yield-limiting contact patterning failure: correlation of simulated image parameters to advanced contact metrology metrics

John Sturtevant, Dyiann Chou

Proceedings Volume 6152, 615209 (2006) https://doi.org/10.1117/12.655192

KEYWORDS: Metrology, Scanning electron microscopy, Optical lithography, Semiconducting wafers, Inspection, Manufacturing, Process modeling, Photomasks, Image processing, Critical dimension metrology

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Electrical failure due to incomplete contacts or vias has arisen as one of the primary modes of yield loss for 130 nm and below designs in manufacturing. Such failures are generally understood to arise from both random and systematic sources. The addition of redundant vias, where possible, has long been an accepted DFM practice for mitigating the impact of random defects. Incomplete vias are often characterized by having a diameter near the target dimension but a depth of less than 100% of target. As such, it is a difficult problem to diagnose and debug in-line, since bright and dark field optical inspection systems cannot typically distinguish between a closed, partially open and fully open contact. Advanced metrology systems have emerged in recent years to meet this challenge, but no perfect manufacturing solution has yet been identified for full field verification of all contacts. Voltage Contrast (VC) SEM metrology biases the wafer to directly measure electrical conductivity after fill / polish, and can therefore easily discern a lack of electrical connection to the underlying conductor caused by incomplete photo, etch, or fill processing. While an entire wafer can in principal be VC scanned, throughput limitations dictate very sparse sampling in manufacturing. SEM profile grading (PG) leverages the rich content of the secondary electron waveform to decipher information about the bottom of the contact. Several authors have demonstrated an excellent response of the Profile Grade to intentional defocus vectors. However, the SEM can only target discreet or single digit groupings of contacts, and therefore requires intelligent guidance to identify those contacts which are most prone to failure, enabling protection of the fab WIP. An a-priori knowledge of which specific contacts in a layout are most likely to fail would prove very useful for proactive inspection in manufacturing. Model based pre-manufacturing verification allows for such knowledge to be communicated to manufacturing. This paper will focus on 130 nm node contact patterning, and will correlate SEM Profile Grade output to the extensive suite of model-based image tags from the Calibre^TM opc-verification engine. With an understanding of which image parameters are most highly correlated to the occurrence of incomplete contact formation for a given process, the process model can be used to automatically direct inspection metrology to those layout instances that pose the highest risk of patterning failure through the lithographic process window. Such an approach maximizes the value content of in-line metrology.

Proceedings Article | 20 March 2006 Paper

Line end optimization through optical proximity correction (OPC): a case study

Dyiann Chou, Ken McAllister

Proceedings Volume 6154, 61543A (2006) https://doi.org/10.1117/12.651455

KEYWORDS: Optical proximity correction, Silicon, Model-based design, Photomasks, Electroluminescence, Critical dimension metrology, Scanning electron microscopy, SRAF, Performance modeling, Semiconducting wafers

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Proceedings Article | 24 May 2004 Paper

Dielectric antireflection layer optimization: correlation of simulation and experimental data

Yiming Gu, Anthony Wang, Dyiann Chou

Proceedings Volume 5375, (2004) https://doi.org/10.1117/12.536560

KEYWORDS: Critical dimension metrology, Semiconducting wafers, Reflectivity, Metals, Manufacturing, Reticles, Dielectrics, Calibration, Antireflective coatings, Coating

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The continuing shrinkage of device size will result in stringent demands on high precision CD control. For example, at 0.13um technology node a typical poly gate size variation should be controlled within +/- 8nm or even smaller. This tight CD budget includes all possible variations which can be from different modules of resist coating track, optical and mechanical parts of exposure tool, non-uniformity of wafer substrate, CD metrology, mask making and so on. Particularly, the residual swing effect after applying an inorganic anti-reflection layer (SiON) still can claim a significant CD budget if not properly optimized. Therefore, how to minimize the residual swing effect still plays important role in CD control. Simulation of reflectivity is considered analytically rigorous and is therefore frequently employed to aid in process development. However, since in manufacturing environments people usually pay more attention to the repeatability of optical metrology tools rather than their accuracies, it is not surprising if some significant discrepancies exist between theoretical and experimental results. Instead of discussing the detail error sources and the tool calibrations, a quick and convenient experimental methodology is introduced to account for such differences and to optimize the film stack composition effectively. In this paper, with the CD variations on metal and poly substrates as examples, an effective combination between the calculations and the experiments is presented in order to minimize the CD swing. We also demonstrate that with the "single wafer swing curve" technique, the residual swing effect can be easily detected and minimized. This methodology provides a possibility to determine the best anti-reflection layer not only from theoretical but also from experimental point of view in manufacturing environments. Since the residual swing effect is a common issue, the results of this paper can be widely used in either manufacturing fabs or experimental labs.

Proceedings Article | 12 June 2003 Paper

Reduction of implantation shadowing effect by dual-wavelength exposure photo process

Yiming Gu, Dyiann Chou, Sang Yun Lee, William Roche, John Sturtevant

Proceedings Volume 5039, (2003) https://doi.org/10.1117/12.485103

KEYWORDS: Deep ultraviolet, Photoresist processing, Semiconducting wafers, Manufacturing, Silicon, Tolerancing, Optical lithography, Ions, Absorption, Ion implantation

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Proceedings Article | 2 June 2003 Paper

Resist compacting under SEM E-Beam

Yiming Gu, Dyiann Chou, John Sturtevant

Proceedings Volume 5038, (2003) https://doi.org/10.1117/12.483432

KEYWORDS: Scanning electron microscopy, Critical dimension metrology, Deep ultraviolet, Image quality, Cadmium, Optical testing, Polymers, Etching, Optics manufacturing, UV optics

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Proceedings Article | 30 July 2002 Paper

Reduction of reflective notching through illumination optimization

James Word, Dyiann Chou, Yiming Gu, John Sturtevant

Proceedings Volume 4691, (2002) https://doi.org/10.1117/12.474566

KEYWORDS: Reflectivity, Photoresist materials, Scanning electron microscopy, Distortion, Semiconducting wafers, Photography, Optical lithography, Bottom antireflective coatings, Photomasks, Critical dimension metrology

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