The EUV lithography started to be used for the high-volume manufacturing of the advanced semiconductor devices such as logic 7nm device and DRAM 1a device by using the conventional EUV masks and blanks with Ta absorber. We developed the new EUV masks and blanks suitable for DRAM 1a and beyond. This new EUV masks and blanks that we developed employs the unique absorber material in order to realize the higher EUV scanner throughput than the conventional EUV masks and blanks, which we think one of advantages of the new EUV masks and blanks. On the other hand, this new EUV masks and blanks can use the similar mask fabrication process to the conventional EUV masks and blanks that we have experiences. In this paper, the fundamental properties of this unique absorber material are reported such as the dry etching performance, the durability to the wet cleaning process and the hydrogen durability. The mask pattern fidelity and the EUV scanner performance are also reported in comparison with the conventional EUV mask and blanks to show the advantage of the new EUV mask and blanks.
The impact of mask defects on wafers has been successfully simulated by KLA’s mask SEM-to-Aerial (S2A) image simulator. The high prediction accuracy, high throughput and low cost have been proven by mask shop production users. S2A generates the reference mask SEM images by rendering the post-OPC design to match with measured mask SEM images containing defects. From the two mask SEM images, defect-free reference absorber contour and defective absorber contour are extracted, and the two contours are used for wafer-level aerial image simulation through EUV scanner conditions. Pass/Fail of %CDE, EPE, etc. are reported by automatically generating measurement cutlines. S2A can be used for wafer prediction for pre/post-repair full height absorber defects using top-down mask SEM images, but it cannot be used for EUV multi-layer buried defects or for partial height residues remaining after repair. KLA and SK hynix have been investigating a solution for this use case using AFM images, which can measure the height error from the buried defect or partial height residue in post-repair mask. In this paper, we will show how measured SEM and AFM images are processed to fit with rendered reference SEM and AFM images. We then show how advanced scanner simulation models are used for determining the wafer printability of mask absorber defects, buried defects and absorber residues. Finally, the predicted wafer impact of the mask defect is compared with wafer SEM images for validation. This approach, named S2A-3D, will help reduce loading on EUV actinic metrology and provide a fast, accurate and cost-effective dispositioning of post-repair EUV defects.
As the pattern size became gradually smaller, the defect detectability of the photomask inspection tool was more improved. For these reasons, we have to repair various defects more precisely. By improving the mask yield through the repair process, we can reduce the cost of mask fabrication. In this study, we studied the defect called quartz damage which distorts the AIMSTM (Arial Image Measurement System) intensity of the repaired pattern and causes the scrap of the photomask. The quartz damage is generally observed when the abnormal defects like particles were repaired in the poor repairing condition. The quartz damage occasionally results in repair errors and affects the AIMS intensity. Currently there is no clear solution for recovering the quartz damage. As a result, it is very difficult to get the high quality photomask if the quartz damage is generated on the photomask. Therefore, it is important to find a method of recovering the quartz damage for producing the high quality photomask. In this paper, we demonstrated that the quartz damage can be recovered through the TEOS (Tetraethoxysilane) gas deposition. Also we investigated the effect on the recovery of the quartz damage of various parameters such as the type and the depth of the quartz damage as well as the repair conditions of the TEOS gas deposition.
To reduce the pattern size in photomask is an inevitable trend because of the minimization of chip size. So it makes a big challenge to control defects in photomask industry. Defects below a certain size that had not been any problem in previous technology node are becoming an issue as the patterns are smaller. Therefore, the acceptable tolerance levels for current defect size and quantity are dramatically reduced. Because these defects on photomask can be the sources of the repeating defects on wafer, small size defects smaller than 200nm should not be ignored any more. Generally, almost defects are generated during develop process and etch process. Especially it is difficult to find the root cause of defects formed during the develop process because of their various types and very small size. In this paper, we studied how these small defects can be eliminated by analyzing the defects and tuning the develop process. There are 3 types of resist defects which are named as follows. The first type is ‘Popcorn’ defect which is mainly occurred in negative resist and exists on the dark features. The second type is ‘Frog eggs’ defect which is occurred in 2nd process of HTPSM and exists on the wide space area. The last type is ‘Spot’ defect which also exists on the wide space area. These defects are generally appeared on the entire area of a plate and the number of these defects is about several hundred. It is thought that the original source is the surface’s hydrophilic state before develop process or the incongruity between resist and developer. This study shows that the optimizing the develop process can be a good solution for some resist defects.
As EUV(Extreme Ultraviolet) Lithography has been delayed because of technical difficulties, ArF-immersion
technology is continued to be utilized in the several future years. To progress constantly chip’s minimization and pattern shrink with ArF wavelength, the adoption of aggressive SRAF(Sub Resolution Assist Feature) is inevitable. This trend is giving the big challenge in Photomask industry such as pattern collapse, pattern wiggling and bending. Generally, the reduction of the resist thickness is being tried to solve these problems. But this approach has the limitation, because of
depending on the margin of etch process. Additionally, finding appropriate resist must be evaluated by a variety of experiments for verifying the stability of the process. According to several papers, the main reason of pattern collapse is
the unbalanced capillary force at drying step in develop process. The capillary stresses (σ) experienced by the resist can
be described as shown in equation (1.1) and Figure 1[1].
The acceptable tolerance level for CD signatures induced by any process step in the mask manufacturing process has
been dramatically reduced with each technology node. Chemical amplified resists (CAR) are used extensively for first layer mask imaging. Therefor a post exposure bake (PEB) process is required after resist exposure, adding yet another potential source of CD signatures. Consequentially, the thermal imprint of the bake process must be further reduced to meet the requirements of future technology nodes.
The influence of the measurement devices (wireless and wired sensor arrays) used to optimize the hotplate, on the performance of the Post Exposure Bake (PEB) process is discussed in [1,2]. A concept of utilizing two wired sensor arrays, with wire connections attached in opposite locations on the sensor array surface, called “Mirror Bake” is introduced. Based on the individual hotplate optimization for each of those two sensor arrays, a combined bake recipe for the multi-zone hotplate is calculated. This method eliminates the systematic temperature non-uniformity introduced by the sensor array hardware, when optimizing the recipes with only one sensor array.
In this paper the “mirror bake” concept is validated by comparing the CD uniformity data of masks manufactured with a PEB process, optimized using a single standard sensor array vs. the “mirror bake” concept. The “mirror bake” concept achieved a CD uniformity improvement of up to 30% (CD range). During this work additional hardware influences from the sensor arrays were identified.
As the feature size is smaller, the overlay budget of lithography for the rigorous manufacturing control becomes so small.
And, overlay accuracy has become more important due to small overlap margin and double patterning process. Recently,
a scanner maker has developed several effective solutions to correct the errors of overlay in field. But, the error induced
by photomask still remains, so the accuracy of photomask image placement is required below than several nm for the HP
3X nm memory device generation. But, current e-beam writers don't meet this specification. There are various sources of
image placement errors. Many papers report their analysis of those errors, so we focus on e-beam charging effect and
compensation. Especially, their compensating methods are too complex to apply to production. So, it is need a simple
way to compensate to image placement errors effectively.
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