While the 10nm logic node is getting ready for High Volume Manufacturing, the industry has started to
make the technology and design choices for the 7nm node. An important question for the industry is
whether to make an irreversible choice for EUV, or to keep both EUV and ArFi multi-patterning as options.
In the former case, it implies that the design rules of several critical layers will be such that the resulting 2D
patterns can only be reliably imaged using EUV. In the latter case, the design rules result in 1D like
patterns which are compatible with ArFi multiple patterning, either by application of cut-/block masks or
by direct print.
In this presentation we will compare the various patterning options by means of an edge placement error
(EPE) based performance analysis. We will explain the advantages and considerations of an EPE budget
compared to a traditional critical dimension uniformity (CDU) budget. The EPE analysis will be applied on
imaging results using critical building blocks or constructs taken from 1D and 2D logic designs. These
include cut mask, line-ends and 2D patterns. The trade-offs between the different designs in terms of
imaging performance will be evaluated, showing the minimum pitch and tip-to-tip that can be supported
based on the required EPE budget.
In the end we will summarize the trade-offs for the N7 design choices based on the EPE assessment.
The NXE:3300B is ASML’s third generation EUV system and has an NA of 0.33 and is positioned at a resolution of 22nm, which can be extended down to 18nm and below with off-axis illumination at full transmission. Multiple systems have been qualified and installed at customers. The NXE:3300B succeeds the NXE:3100 system (NA of 0.25), which has allowed customers to gain valuable EUV experience. It is expected that EUV will be adopted first for critical Logic layers at 10nm and 7nm nodes, such as Metal-1, to avoid the complexity of triple patterning schemes using ArF immersion. In this paper we will evaluate the imaging performance of (sub-)10nm node Logic M1 on the NXE:3300B EUV scanner. We will show the line-end performance of tip-to-tip and tip-to-space test features for various pitches and illumination settings and the performance enhancement obtained by means of a 1st round of OPC. We will also show the magnitude of local variations. The Logic M1 cell is evaluated at various critical features to identify hot spots. A 2nd round OPC model was calibrated of which we will show the model accuracy and ability to predict hot spots in the Logic M1 cell. The calibrated OPC model is used to predict the expected performance at 7nm node Logic using off-axis illumination at 16nm minimum half pitch. Initial results of L/S exposed on the NXE:3300B at 7nm node resolutions will be shown. An outlook is given to future 0.33 NA systems on the ASML roadmap with enhanced illuminator capabilities to further improve performance and process window.
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