This paper presents a Dynamic Range improvement technique which is specially well-suited to be implemented in
Focal Plane Processors (FPP) due to its very limited computing requirements since only local memories, little digital
control and a comparator are required at the pixel level. The presented algorithm employs measurements during exposure
time to create a 4-bit non-linear image whose histogram determines the shape of the tone-mapping curve which is applied
to create the final image. Simulations results over a highly bimodal 120dB image are presented showing that both the
highly and poorly illuminated parts of the image keep a sufficient level of details.
KEYWORDS: Transceivers, Silicon, Amplifiers, Modulators, Telecommunications, Analog electronics, Standards development, Global system for mobile communications, Phase only filters, Evolutionary algorithms
In the last few years, we are witnessing the convergence of more and more communication capabilities into a single
terminal. A basic component of these communication transceivers is the multi-standard Analog-to-Digital-Converter (ADC). Many systematic, partially automated approaches for the design of ADCs dealing with a single communication standard have been reported. However, most multi-standard converters reported in the literature follow an ad-hoc approach, which do not guarantee either an efficient occupation of silicon area or its power efficiency in the different standards. This paper aims at the core of this problem by formulating a systematic design approach based on the following key elements:
(1) Definition of a set of metrics for reconfigurability: impact in area and power consumption, design complexity and
performances; (2) Definition of the reconfiguration capabilities of the component blocks at different hierarchical levels,
with assessment of the associated metrics; (3) Exploration of candidate architectures by using a combination of simulated
annealing and evolutionary algorithms; (4) Improved top-down synthesis with bottom-up generated low-level design
information. The systematic design methodology is illustrated via the design of a multi-standard &Sgr;&Dgr; modulator meeting the
specifications of three wireless communication standards.
This paper describes the design of a programmable stand-alone system for real time vision pre-processing tasks. The system's architecture has been implemented and tested using an ACE16k chip and a Xilinx xc4028xl FPGA. The ACE16k chip consists basically of an array of 128x128 identical mixed-signal processing units, locally interacting, which operate in accordance with single instruction multiple data (SIMD) computing architectures and has been designed for high speed image pre-processing tasks requiring moderate accuracy levels (7 bits). The input images are acquired using the optical input capabilities of the ACE16k chip, and after being processed according to a programmed algorithm, the images are represented at real time on a TFT screen. The system is designed to store and run different algorithms and to allow changes and improvements. Its main board includes a digital core, implemented on a Xilinx 4028 Series FPGA, which comprises a custom programmable Control Unit, a digital monochrome PAL video generator and an image memory selector. Video SRAM chips are included to store and access images processed by the ACE16k. Two daughter boards hold the program SRAM and a video DAC-mixer card is used to generate composite analog video signal.
Setting specifications for the electronic implementation of biological neural-network-like vision systems on-chip is not straightforward, neither it is to simulate the resulting circuit. The structure of these systems leads to a netlist of more than 100.000 nodes for a small array of 100x150 pixels. Moreover, introducing an optical input in the low level simulation is nowadays not feasible with standard electrical simulation environments. Given that, to accomplish the task of integrating those systems in silicon to build compact, low power consuming, and reliable systems, a previous step in the standard analog electronic design flux should be introduced. Here a methodology to make the translation from the biological model to circuit-level specifications for electronic design is proposed. The purpose is to include non ideal effects as mismatching, noise, leakages, supply degradation, feedthrough, and temperature of operation in a high level description of the implementation, in order to accomplish behavioural simulations that require less computational effort and resources. A particular case study is presented, the analog electronic implementation of the locust’s Lobula Giant Movement Detector (LGMD), a neural structure that fires a collision alarm based on visual information. The final goal is a collision threat detection vision system on-chip for automotive applications.
The interest in tactile sensors is increasing as their use in complex unstructured environments is demanded, like in telepresence, minimal invasive surgery, robotics etc. The matrix of pressure data these devices provide can be managed with many image processing algorithms to extract the required information. However, as in the case of vision chips or artificial retinas, problems arise when the array size and the computation complexity increase. Having a look to the skin, the information collected by every mechanoreceptor is not carried to the brain for its processing, but some complex pre-processing is performed to fit the limited throughput of the nervous system. This is specially important for high bandwidth demanding tasks. Experimental works report that neural response of skin mechanoreceptors encodes the change in local shape from an offset level rather than the absolute force or pressure distributions. This is also the behavior of the retina, which implements a spatio-temporal averaging. We propose the same strategy in tactile preprocessing, and we show preliminary results when it faces the detection of the slip, which involves fast real-time processing.
In this paper a bioinspired algorithm for collision detection is proposed, based on previous models of the locust (Locusta migratoria) visual system reported by F.C. Rind and her group, in the University of Newcastle-upon-Tyne. The algorithm is suitable for VLSI implementation in standard CMOS technologies as a system-on-chip for automotive applications. The working principle of the algorithm is to process a video stream that represents the current scenario, and to fire an alarm whenever an object approaches on a collision course. Moreover, it establishes a scale of warning states, from no danger to collision alarm, depending on the activity detected in the current scenario. In the worst case, the minimum time before collision at which the model fires the collision alarm is 40 msec (1 frame before, at 25 frames per second). Since the average time to successfully fire an airbag system is 2 msec, even in the worst case, this algorithm would be very helpful to more efficiently arm the airbag system, or even take some kind of collision avoidance countermeasures. Furthermore, two additional modules have been included: a "Topological Feature Estimator" and an "Attention Focusing Algorithm". The former takes into account the shape of the approaching object to decide whether it is a person, a road line or a car. This helps to take more adequate countermeasures and to filter false alarms. The latter centres the processing power into the most active zones of the input frame, thus saving memory and processing time resources.
This paper describes the architecture and retino-topic unit of a bio-inspired vision chip intended for automotive applications. The chip contains an array of 100X150 sensors which are able to capture high dynamic range (HDR) images, with a programmable compressive characteristic. The chip also incorporates a mechanism for adaptation of the global exposition time to the average illumination conditions. Average values are evaluated over image areas which are programmable by the user. In addition to the HDR pixel, every retino-topic unit in the array incorporates digital memory for three 6-bit pixel values (18-bits), as required for the implementation of a bionspired computing model for collisions detection which has been developed in the framework of a multidisciplinary European research project. All processing steps are executed off-chip, though we are currently working in the design of tiny digital processors (one per column) which will allow for running the whole model on-chip in a future version of this prototype. The chip has been designed in a 0.35μm 2P-4M technology and maintains its correct operation in extreme temperature conditions (from -40°C to 110°C).
This paper describes an optical sensor interface designed for a programmable mixed-signal vision chip. This chip has been designed and manufactured in a standard 0.35μm n-well CMOS technology with one poly layer and five metal layers. It contains a digital shell for control and data interchange, and a central array of 128 × 128 identical cells, each cell corresponding to a pixel. Die size is 11.885 × 12.230mm2 and cell size is 75.7μm × 73.3μm. Each cell contains 198 transistors dedicated to functions like processing, storage, and sensing. The system is oriented to real-time, single-chip image acquisition and processing. Since each pixel performs the basic functions of sensing, processing and storage, data transferences are fully parallel (image-wide). The programmability of the processing functions enables the realization of complex image processing functions based on the sequential application of simpler operations. This paper provides a general overview of the system architecture and functionality, with special emphasis on the optical interface.
In this paper a programmable imager with averaging capabilities will be described which is intended for averaging of different groups or sets of pixels formed by n X n kernels, n X m kernels or any group of randomly- selected pixels across the array. This imager is a 64 X 64 array which uses passive pixels with electronic shutter and anti-blooming structure that can be randomly accessed. The read-out stage includes a sole charge amplifier with programmable gain, a sample-and-hold structure and an analog buffer. This read-out structure is different from other existing imagers with variable resolution since it uses a sole charge amplifier, whereas the conventional structure employs an opamp per column plus another global opamp. this architecture allows a reduction of the fixed-pattern noise observed in standard imagers. The prototype also includes an analog to digital converter which provides the digital output of the images.
This paper describes a full-custom mixed-signal chip which embeds distributed optical signal acquisition, digitally- programmable analog parallel processing, and distributed image memory--cache--on a common silicon substrate. The paper briefly describes the chip architecture and focus mostly on presenting experimental evidence of the chip functionality. Multiscale low-pass and high-pass filtering of gray-scale images, analog edges extraction, image segmentation, thresholded gradient detection, mathematical morphology operations, shortest path detection in a labyrinth, skeletonizing, image reconstruction, several non- linear type image processing tasks like absolute value calculation of gray-scale gradient detection and real-time motion detection in QCIF video sequences are some of the very interesting applications that have been demonstrated as available when using the prototype.
Due to their local connectivity and wide functional capabilities, cellular nonlinear networks (CNN) are excellent candidates for the implementation of image processing algorithms using VLSI analog parallel arrays. However, the design of general purpose, programmable CNN chips with dimensions required for practical applications raises many challenging problems to analog designers. This is basically due to the fact that large silicon area means large development cost, large spatial deviations of design parameters and low production yield. CNN designers must face different issues to keep reasonable enough accuracy level and production yield together with reasonably low development cost in their design of large CNN chips. This paper outlines some of these major issues and their solutions.
The infrared response of polycrystalline and epitaxial CoSi2/Si Schottky diodes with similar silicide thickness has been measured. For the polycrystalline diodes the quantum efficiency is found to be two times higher than for the epitaxial diodes, although both types of diodes present very similar barrier height. The observed improvement is attributed to grain boundary scattering of the excited carriers.
A CoSi2/strained-Si1-xGex-Schottky barrier detector is proposed for detection of infrared radiation in the 3 - 5 micrometers window. It could be a substitute for PtSi/Si-Schottky barrier detectors, which have already been integrated with readout electronics, but which imply the disadvantage of having the metal Pt in the line as a possible source of contamination. A silicidation study on strained Si1-xGex-layers with sacrificial Si-layers on top has been carried out to realize CoSi2/strained-Si1-xGex-interfaces, which will form the heart of the detector. The possibilities to integrate this detector with readout electronics are critically reviewed. First CoSi2/Si1-xGex-detectors have been processed which yield barrier heights as low as 229 meV.
A 512 pixel truly linear infrared (IR) charge coupled device (CCD) with Schottky barrier sensors and buttable edges has been developed, incorporating three different silicides working in the front-side illumination mode. The main differences between these silicides are the cut- off wavelength and the operating temperature. CoSi2 and NiSi show a cut-off wavelength of about 2.8 micrometers allowing an operating temperature of 150 K and passive cooling, whereas PtSi has a cut-off wavelength of about 6 micrometers working at 77 K. All three devices present a good photoresponse uniformity along the sensor row and also a good noise behavior.