Dr. Emmanuel Dupuy Profile

Dr. Emmanuel Dupuy

at imec

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Publications (4)

Proceedings Article | 23 March 2020 Presentation + Paper

FEOL dry etch process challenges of ultimate FinFET scaling and next generation device architectures beyond N3

Z. Tao, L. Zhang, E. Dupuy, B. T. Chan, E. Altamirano-Sanchez, F. Lazzarino

Proc. SPIE. 11329, Advanced Etch Technology for Nanopatterning IX

KEYWORDS: Etching, Optical lithography, Silicon, Fin field effect transistors, Front end of line, Dry etching, Field effect transistors, Gallium arsenide, Plasma etching, Nanowires

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FinFETs have demonstrated significant performance improvement compared to planar devices, because of its superior short channel control and higher driving capability at a much smaller footprint. It has become the mainstream technology in CMOS industry since N20 node onward. Contact Poly Pitch (CPP) scaling used to be the main driving force in extending Moore’s law. However, severe limitations are foreseen from N3 node in terms of electrical performance, process requirements and manufacturing complexity. At N3 node, both fin and gate pitches are expected to reach their ultimate values, respectively 21 nm and 42 nm. Therefore, complex plasma etching processes using advanced plasma pulsing modes or atomic layer etching (ALE) are deployed to achieve high aspect ratio patterning capability with a detrimental effect on both process control and throughput. As an alternative, device architecture innovation will become the main scaling driving force for N3 node and beyond. 2D scaling like horizontal Gate-All-Around (GAA) devices, such as nanosheet (NS) and forksheet (FS) have demonstrated the potential for further device performance improvement [1,2]. The major NS patterning challenges are the SiGe lateral etch in the Si/SiGe superlattice stack and severe depth micro-loading due to the etch rate difference of SiGe and Si. In addition, 3D hybrid device architectures like Complementary FET (CFET) and Surrounding-Gate-Transistors (SGT) are proposed as revolutionary innovations to scale the devices in the vertical direction. For CFET devices, the N/P separation is moved to the vertical direction by stacking nMOS on top of pMOS or vice versa to achieve aggressive device scaling. This requires extremely high aspect ratio fin and gate patterning compared to horizontal-GAA NS devices. For SGT device, the channel is switched to the vertical direction, which can decouple the Gate length (Lg) from CPP scaling and eliminate the diffusion break to deeply scale the cell size. High aspect ratio vertical nanowire (NW) and direct metal gate etching with tight pitch are the new FEOL patterning challenges for the fabrication of SGT vertical devices.

Proceedings Article | 17 March 2015 Paper

Spectral analysis of the line-width and line-edge roughness transfer during self-aligned double patterning approach

Emmanuel Dupuy, E. Pargon, M. Fouchier, H. Grampeix, J. Pradelles, M. Darnon, P. Pimenta-Barros, S. Barnola, O. Joubert

Proc. SPIE. 9428, Advanced Etch Technology for Nanopatterning IV

KEYWORDS: Line edge roughness, Line width roughness, Plasma, Etching, Critical dimension metrology, Plasma etching, Silicon, Oxygen, Photoresist processing, Neodymium

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Proceedings Article | 28 May 2013 Paper

The photonic nanowire: an emerging platform for highly efficient single-photon sources for quantum information applications

Niels Gregersen, Mathieu Munsch, Nitin Malik, Joël Bleuse, Emmanuel Dupuy, Adrien Delga, Jesper Mørk, Jean-Michel Gérard, Julien Claudon

Proc. SPIE. 8749, Quantum Information and Computation XI

KEYWORDS: Surface plasmons, Mirrors, Quantum information, Quantum efficiency, Gaussian beams, Interfaces, Metals, Semiconductors, Nanowires, Photonic nanostructures

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Proceedings Article | 14 March 2013 Paper

A photonic nanowire trumpet for interfacing a quantum dot and a Gaussian free-space mode

Niels Gregersen, Mathieu Munsch, Nitin Malik, Joël Bleuse, Emmanuel Dupuy, Adrien Delga, Jesper Mørk, Jean-Michel Gérard, Julien Claudon

Proc. SPIE. 8619, Physics and Simulation of Optoelectronic Devices XXI

KEYWORDS: Quantum dots, Gaussian beams, Surface plasmons, Mirrors, Quantum efficiency, Interfaces, Semiconductors, Gallium arsenide, Nanowires, Photonic nanostructures

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