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In this paper, a new approach named Contour-based 2D Metrology will be introduced as assistance for the repair processes of such challenging micro defects. Both CDSEM images of defect and reference are input for extracting; then contour-based patterns are overlapped for each other and compared with GDS as well, to describe quantitative differences for each micro area. Assisted with such rigorous and comprehensive data analysis, micro defects can be accurately positioned according to Aims Results and repair processes would be proceeding.
This paper investigates a pattern contour based solution for 2D structure performance evaluation. The basic contours of GDS and CD-SEM image are extracted, overlapped and processed and then the edge roughness of SEM contour and the bias between the above two kinds of contour are adopted on 2D individual pattern performance’s statistics. By utilizing this solution, the 2D pattern quality can be described quantitatively as two main aspects, shape and size with the results of edge roughness and bias. Generalize this solution, the 2D pattern’s uniformity, mean size, or other performances, can be evaluated quantitatively in the similar way as well. This solution calculation bases on pattern contour, therefore the measure pattern is not restricted by its shape.
In this paper we propose a novel method of mask registration correction, which can be applied before mask writing based on mask exposure map, considering the factors of mask chip layout, writing sequence, and pattern density distribution. Our experiment data show if pattern density on the mask keeps at a low level, in-die mask registration residue error in 3sigma could be always under 5nm whatever blank type and related writer POSCOR (position correction) file was applied; it proves random error induced by material or equipment would occupy relatively fixed error budget as an error source of mask registration. On the real production, comparing the mask registration difference through critical production layers, it could be revealed that registration residue error of line space layers with higher pattern density is always much larger than the one of contact hole layers with lower pattern density. Additionally, the mask registration difference between layers with similar pattern density could also achieve under 5nm performance. We assume mask registration excluding random error is mostly induced by charge accumulation during mask writing, which may be calculated from surrounding exposed pattern density. Multi-loading test mask registration result shows that with x direction writing sequence, mask registration behavior in x direction is mainly related to sequence direction, but mask registration in y direction would be highly impacted by pattern density distribution map. It proves part of mask registration error is due to charge issue from nearby environment. If exposure sequence is chip by chip for normal multi chip layout case, mask registration of both x and y direction would be impacted analogously, which has also been proved by real data. Therefore, we try to set up a simple model to predict the mask registration error based on mask exposure map, and correct it with the given POSCOR (position correction) file for advanced mask writing if needed.
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