Operating maskless, massively parallel electron beam direct write (MEBDW) is an attractive alternative to optical lithography in micro and nano device manufacturing. Mapper Lithography develops MEBDW tools able to pattern wafers, for application nodes down to 28nm, with a throughput around one wafer per hour. A prototype tool from this series, named FLX-1200, is installed in the CEA-Leti clean room. This paper reviews the current performances of this prototype and the methodology used to measure them. On standardized exposure, consisting of 100 fields of 5×5mm2 exposed, in less than one hour, on 300mm silicon wafers, we obtained CD uniformity below 10nm (3σ) and LWR of 4.5nm for 60nm half pitch dense lines. We also demonstrate capability of 15nm and 25nm (3σ) for stitching and overlay errors respectively.
KEYWORDS: Overlay metrology, Metrology, Electron beam lithography, Lenses, Distance measurement, Electron beams, Raster graphics, Semiconducting wafers, Time metrology, Process control
One of the metrology challenges for massively parallel electron beams is to verify that all the beams that are used perform within specification. The Mapper FLX-1200 platform exposes fields horizontally segmented in 2.2 μm-wide stripes. This yields two parameters of interest: overlay is the registration error with respect to a previous layer, and stitching is the registration error between the stripes. This paper presents five novel overlay targets and one novel stitching target tailored for Mapper’s needs and measured on KLA-Tencor Archer 600 image based overlay (IBO) platform. The targets have been screened by exposure of a variable shaped electron beam lithography machine (Vistec VSB 3054 DW) on two different stacks: resist-to-resist and resist-to-etched silicon, both as a trilayer stack. These marks attain a total measurement uncertainty (TMU) down to 0.3 nm and move-and-measure (MAM) time down to 0.3 seconds for both stacks. The stitching targets have an effective TMU of 0.4 nm and a MAM time of 0.75 seconds. In a follow up experiment, the two best performing overlay targets have been incorporated in an exposure by a Mapper FLX-1200. With the new stack a TMU of 0.3 nm and MAM time of 0.35 s have been attained. For 107 out of 140 selected stripes the slope was constant within 2.5%, the offset smaller than 0.5 nm and correlation coefficient R2 > 0.98.
Mapper has installed its first product, the FLX–1200, at CEA-Leti in Grenoble (France). This is a maskless lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. The FLX-1200, containing 65,000 parallel electron beams in a 13mm x 2mm electron optics slit, is capable of patterning any resolution and any different type of structure all the way down to 28 nm node patterns. As of August 2017 the FLX-1200 has a fully operational electron optics column, including a 65,000 beam blanker. In this paper the latest technical achievements of the FLX-1200 have been described: beam current is at 80% of FLX-1300 target (85 minutes per wafer). For 42nm hp dense lines a CDu of 8nm 3σ and a LWR of 5nm 3σ has been demonstrated. The stitching error is 12nm μ+3σ and regarding overlay a 15nm capability demonstrated, provided matching strategy is implemented and the mirror map is calibrated.
Mapper Lithography has introduced its first product, the FLX–1200, which is installed at CEA-Leti in Grenoble (France). This is a mask less lithography system, based on massively parallel electron-beam writing with high-speed optical data transport for switching the electron beams. This FLX platform is initially targeted for 1 wph performance for 28 nm technology nodes, but can also be used for less demanding imaging. The electron source currently integrated is capable of scaling to 10 wph at the same resolution performance, which will be implemented by gradually upgrading the illumination optics. The system has an optical alignment system enabling mix-and-match with optical 193 nm immersion systems using standard NVSM marks. The tool at CEA-Leti is in-line with a Sokudo Duo clean track. Mapper Lithography and CEA-Leti are working in collaboration to develop turnkey solution for specific applications.
At previous conferences we have presented imaging results including 28nm node resolution, cross wafer CDu of 2.5nm 3 and a throughput of half a wafer per hour, overhead times included. At this conference we will present results regarding the overlay performance of the FLX-1200.
In figure 2 an initial result towards measuring the overlay performance of the FLX-1200 is shown. We have exposed a wafer twice without unloading the wafer in between exposures. In the first exposure half of a dense dot array is exposed. In the second exposure the remainder of the dense dot array is exposed. After development the wafer has been inspected using a CD-SEM at 480 locations distributed over an area of 100mm x 100mm. For each SEM image the shift of the pattern written in the first exposure relative to the pattern written in the second exposure is measured. Cross wafer this shift is 7 nm u+3s in X and 5 nm u+3s in Y. The next step is to evaluate the impact of unloading and loading of the wafer in between exposures. At the conference the latest results will be presented.
The MATRIX platform integrates new types of modules for handling and alignment capability and this represents two new and innovative aspects for multi-beam lithography. Results on performances in terms of robustness of the different modules in real manufacturing conditions, including the interface of the MATRIX platform with the SOKUDO DUO track will be reported. A new type of alignment solution was developed by MAPPER. This paper will show the first results on alignment sensor repeatability. Preliminary results on the overlay performance of the MATRIX platform will be presented and discussion will be engaged to position the MAPPER alignment concept with respect to the ITRS roadmap expectations.
KEYWORDS: Electron beam lithography, Semiconducting wafers, Collimators, Electron beams, Wafer-level optics, Lithography, High volume manufacturing, Data corrections, Maskless lithography, Switching
MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam
writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made
with a throughput of 10 wafers per hour. By clustering several of these systems together high throughputs can be realized
in a small footprint. This enables a highly cost-competitive solution for either direct patterning or complementary
patterning approach, [1, 2].
For a 10 wph throughput per unit MAPPER will use 13,260 parallel electron beams, delivering 170 μA to the wafer. To
realize this large current at the wafer MAPPER uses its patterned beam approach where each beam consists of 49
subbeams [3].
MAPPER is currently realizing its MATRIX platform. This system is one unit in the cluster depicted above and will
have a capability of 10 wph (containing the patterned beams approach) and have full overlay capability. One 10 wph unit
will have a footprint of 1.1 m x 1.65m.
This paper will provide an overview of the development status of this MATRIX platform.
C. van den Berg, G. de Boer, S. Boschker, E. Hakkennes, G. Holgate, M. Hoving, R. Jager, J. Koning, V. Kuiper, Yue Ma, I. van Mil, H. W. Mook, T. Ooms, T. van de Peut, S. Postma, M. Sanderse, P. Scheffers, E. Slot, A. Tudorie, A. M. Valkering, N. Venema, N. Vergeer, A. Weirsma, S. Woutersen, M. Wieland, B. Kampherbeek
Currently, three MAPPER multi-electron beam lithography tools are operational. Two are located at customers, TSMC
and LETI, and one is located at MAPPER. The tools at TSMC and LETI are used for process development. These tools
each have 110 parallel electron beams and have demonstrated sub-30 nm half pitch resolution in chemically amplified
resists.
One important step towards the high volume tool is the capability to stitch the exposure of one electron beam to the next.
The pre-alpha tool at MAPPER has been upgraded with an interferometer to enable exposures with a scanning stage and
demonstrate first beam-to-beam stitching. A scan of 200 micrometers has been used to create a stitch area of 50 x 3
microns. The stitch error over all stitches was found to be below 25 nm.
The electron beam position stability during the 10 seconds required for beam-to-beam stitching showed a contribution to
the stitch error of 2.3 nm. The beam separation measurement, used to correct the static error, adds about 2.2 nm and the
stage stability and linearity adds another 5 nm in the scan (interferometer) direction. In the perpendicular direction the
stage instability gives the largest contribution to the stitch error (15 nm) due to the use of capacitive sensors.
Overall, the electron beam stability and the beam position correction method work correctly and with sufficient accuracy
for the high volume tool, 'Matrix'. The wafer stage for the Matrix system will incorporate full interferometer control to
attain the needed positioning accuracy and stability.
MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam
writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made
with a throughput of 10-20 wafers per hour. By clustering several of these systems together high throughputs can be
realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV
alternatives[1].
In 2009 MAPPER shipped two systems one to TSMC and one to CEA-Leti. Both systems will be used to verify the
applicability of MAPPER's technology for CMOS manufacturing.
This paper presents a status update on the development of the MAPPER system over the past year. First an overview will
be presented how to scale the current system to a 10 wph machine which can consequently be used in a cluster
configuration to enable 100 wph throughputs.
Then the results of today's (pre-) alpha systems with 300 mm wafer capability are presented from the machines at
MAPPER, TSMC and CEA-Leti.
E-beam maskless lithography is a potential solution for 32-nm half-pitch (HP) node and beyond. The major concern
to implement it for mass production is whether its throughput can reach a production-worthy level. Without violating the
law of physics using unrealistic e-beam current, parallelisms in the writing beams and the data path are a few possible
solutions to achieve such high productivity. It has been proposed to realize throughput greater than 10 wafers per hour
(WPH) from a single column with >10,000 e-beams writing in parallel, or even greater than 100 WPH by further
clustering multiple columns within an acceptable tool footprint. The MAPPER concept contains a CMOS-MEMS
blanker array supported by high-speed optical data-path architecture to simultaneously control this high number of
beams, switching them on and off independently.
The MAPPER pre-α tool with a 110-beam 5-keV column and a 300-mm wafer stage has been built and is ready for
imaging test. In this paper, the resist imaging results of 110-beam parallel raster-scan writing for 32-nm logic circuit
layout on 300-mm wafer is shown. The challenges of implementing multiple e-beam maskless lithography (MEBML2)
in mass production environment, including illumination, focusing, and CD uniformity, are discussed.
V. Kuiper, B. Kampherbeek, M. Wieland, G. de Boer, G. ten Berge, J. Boers, R. Jager, T. van de Peut, J. J. M. Peijster, E. Slot, S. W. H. K. Steenbrink, T. Teepen, A. H. V. van Veen
Maskless electron beam lithography, or electron beam direct write, has been around for a long time in the semiconductor industry and was pioneered from the mid-1960s onwards. This technique has been used for mask writing applications as well as device engineering and in some cases chip manufacturing. However because of its relatively low throughput compared to optical lithography, electron beam lithography has never been the mainstream lithography technology. To extend optical lithography double patterning, as a bridging technology, and EUV lithography are currently explored. Irrespective of the technical viability of both approaches, one thing seems clear. They will be expensive [1].
MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these columns together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives. In 2007 MAPPER obtained its Proof of Lithography milestone by exposing in its Demonstrator 45 nm half pitch structures with 110 electron beams in parallel, where all the beams where individually switched on and off [2].
In 2008 MAPPER has taken a next step in its development by building several tools. A new platform has been designed and built which contains a 300 mm wafer stage, a wafer handler and an electron beam column with 110 parallel electron beams. This manuscript describes the first patterning results with this 300 mm platform.
Maskless electron beam lithography, or electron beam direct write, has been around for a long time in the semiconductor industry and was pioneered from the mid-1960s onwards. This technique has been used for mask writing applications as well as device engineering and in some cases chip manufacturing. However because of its relatively low throughput compared to optical lithography, electron beam lithography has never been the mainstream lithography technology. To extend optical lithography double patterning, as a bridging technology, and EUV lithography are currently explored. Irrespective of the technical viability of both approaches, one thing seems clear. They will be expensive [1].
MAPPER Lithography is developing a maskless lithography technology based on massively-parallel electron-beam writing with high speed optical data transport for switching the electron beams. In this way optical columns can be made with a throughput of 10-20 wafers per hour. By clustering several of these columns together high throughputs can be realized in a small footprint. This enables a highly cost-competitive alternative to double patterning and EUV alternatives. In 2007 MAPPER obtained its Proof of Lithography milestone by exposing in its Demonstrator 45 nm half pitch structures with 110 electron beams in parallel, where all the beams where individually switched on and off [2].
In 2008 MAPPER has taken a next step in its development by building several tools. The objective of building these tools is to involve semiconductor companies to be able to verify tool performance in their own environment. To enable this, the tools will have a 300 mm wafer stage in addition to a 110-beam optics column. First exposures at 45 nm half pitch resolution have been performed and analyzed. On the same wafer it is observed that all beams print and based on analysis of 11 beams the CD for the different patterns is within 2.2 nm from target and the CD uniformity for the different patterns is better than 2.8 nm.
E. Slot, M. Wieland, G. de Boer, P. Kruit, G. ten Berge, A. Houkes, R. Jager, T. van de Peut, J. Peijster, S. Steenbrink, T. Teepen, A. van Veen, B. Kampherbeek
MAPPER Lithography is developing a maskless lithography technology. The technology combines massively-parallel
electron-beam writing with high speed optical data transport used in the telecommunication industry. The electron optics
generates 13,000 electron beams that are focused on the wafer by electrostatic lens arrays which are manufactured by
using MEMS manufacturing techniques. Each beam has its own optical column to avoid a central cross-over. This
secures high throughput (> 10 wafers per hour) at high resolution (< 45 nm half pitch). The 13,000 e-beams are
generated by splitting up a single electron beam that originates from a single electron source and are finally accelerated
to 5 kV to expose the resist on the wafer. The e-beams are arranged in such a way that they form a rectangular slit with a
width of 26 mm, the same width of a field in an optical stepper. During exposure the e-beams are deflected over 2 μm
perpendicular to the wafer stage movement. This means that with one scan of the wafer a full field of 26 mm x 33 mm
can be exposed. During the simultaneous scanning of the wafer and deflection of the electron beams the beams are
switched on and off by 13,000 light signals, one for each e-beam. The light beams are generated in a data system that
contains the chip patterns in a bitmap format. This bitmap is divided over 13,000 data channels and streamed to the ebeams
at 1-10 GHz. This paper will explain the design drivers behind the system and provide more detail on the current
design. Finally, results of our technology Demonstrator are presented, showing the viability of MAPPER's concept.
The Multiple E-beam Direct Write (MEBDW) technology has been considered a promising solution for the next
generation lithography to delineate 32-nm half-pitch and beyond. A low-energy, say 5 keV, e-beam direct writing system
has advantages in lower exposure dosage, less heating effect on resist, and less damage to devices underneath, comparing
with a high energy one, such as 50 keV or 100 keV. However, the low-energy electron-beam is easily blurred due to
forward scattering in the substrate due to its shallow penetration and hence loses resolution. In this paper, variables
affecting patterning fidelity of a raster-scan MEBDW system are investigated.
In order to realize a MEBDW system with acceptable throughput, a relatively large beam size is chosen for sufficient
beam current to sustain throughput while maintaining enough resolution. The imaging resolution loss and the proximity
effect, due to beam blurring through the resist, have been observed. The in-house software MOSES, incorporating the
Monte Carlo simulation and the Double Gaussian model was used to evaluate 1-D and 2-D pattern fidelity with various
exposure conditions. The line width roughness, which represents 1-D fidelity, was evaluated on 32-nm dense lines.
Pattern fidelity of 2-D features such as the zigzag poly line and dense metal patterns was also examined. The impact to
LWR of using the edge dithering method, instead of dosage modulation, to control the line width accuracy beyond the
pixel size was studied.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.