Sub-resolution assistance feature (SRAF) has become one of popular resolution enhancement technique because it is
the most easily applicable technique that can be adopted for sub-65 nm node technology. The SRAF can be realized, for
example, by locating lines having width below resolution limit around isolated feature. With the SRAF, intensity profile
of the isolated feature will be modified to dense-like one and, as a result, focus response of the isolated feature can be
improved up to dense feature level. Previous works on SRAF have focused mainly on the critical dimension (CD) margin
window. However, CD margin window is not sufficient to evaluate optimum SRAF configuration because process
margin degradation due to irregular pattern profile such as line edge roughness (LER) would become more prominent as
technology node goes beyond sub-65nm node. Therefore, appropriate methodology to optimize SRAF configuration both
for CD margin window and pattern profile is indispensable for those applications.
In this paper, we focus on the impact of SRAF configuration to pattern profile as well as CD margin window. The
SRAF configuration was adjusted by varying assistance feature to main feature distance and pitch of the assistance
features at mask level. Pattern profile was investigated by measuring LER with varying assistance feature parameters
quantitatively. From the results, we prove the impact of SRAF configuration both on pattern profile and CD margin
window. We also show that the experimental data can easily be predicted by calibrating aerial image simulation results to
measured LER. As a conclusion, we suggest methodology to set up optimum SRAF configuration with regard to both
CD margin window and pattern profile.
We discussed to KrF process extension for 90 nm technology node. The continuous shrinkage of critical dimensions on
sub 130 nm devices becomes a key point to improve process margin with pattern resolution problem for lithography.
Recently, according to development demand of high density and high integration device, it is tendency that the shrink
rate of design rule is gradually accelerated. It is difficult to develop with image contrast problem around k1=0.25 which
is a theoretical process limit region. We need to technology development which is available to having resolution for sub
90nm line and space by using KrF lithography not by using ArF lithography.
In generally, KrF have not been used in nano-process such as 90nm technology. In this study, however, we can apply
the KrF in 90nm technology by means of minimizing the error range in the nano-process, optimizing the process, and
extending the process margin. This Application of KrF in 90nm technology results in elimination of additional
investment for development of 90nm technology.
Finally, we will show which simulation and experimental results such as normalized image log slope, pupil plane,
image of focus variation, process window, top view image, photo resist and etch profile, and pitch linearity.
Recently, in order to increase the number of transistors in wafer by small feature size, optical lithography has
been changed to low wavelength from 365nm to 193nm and high NA of 0.93. And further wavelength is aggressively
shifting to 13.5nm for more small feature size, i.e., Extreme Ultra Violet Lithography(EUVL), a kind of Next Generation
Lithography(NGL)1. And other technologies are developed such as water immersion(193nm) and photo resist Double
Patterning(DP). Immersion lens system has high NA up to 1.3 due to high n of water(n=1.44 at 193nm), the parameter k1
is process constant, but 0.25 is a tough limit at a equal line and space, if we use immersion lens with 193nm wavelength
than limit of resolution is 37nm. Especially, Double Exposure Technique(DET) process is widely studied because of the
resolution enhancement ability using a same material and machine, despite of process complication. And SADP(Self
Aligned Double Patten) is newly researched for overlay and LER(Line Edge Roughness) enhancement.
In this paper, we illustrate the feasibility of the shift double pattern for 65nm-node flash using a 193nm light
dipole source and the possibility of decrease minimum feature size using a property of silicon shrinkage during thermal
In resolution limited lithography process, the image deformation is getting severer. This is very important area where
we need to fully understand and improved since the image deformation is directly giving poor CD control effect.
Especially, contact hole image will be more sensitive since it has lower k1 factor that line and spaced pattern. This image
deformation of contact hole can give some severe electrical fail due to not opened contact. In our case, we observed
some critical failure mode of diagonal induced by abnormal contact hole shape of rough edge.
In this paper, we investigate how deformed contact hole image impacted on degradation of device performance in
electrical properties and yield and how we can improve it. To quantitatively analyze image deformation of contact hole,
we recommend new measurement method first. This new measurement gives exact image deformation amount at
different experimental conditions.
Finally, we will show how experimental conditions such as soft bake temperature, post expose bake temperature,
hardening bake temperature, illumination condition and mask bias change image deformation of contact hole.
In lithography process, resolution enhancement technique (RET) which makes us use same lithographic
equipments and materials is one of most important area to enhance development speed of device. The studies for RET
have widely been done and the examples of RET are modified illumination, phase shifted mask and double exposure.
The most studies have been done in lithography area. We think that area of RET study is not only lithography but also
overall patterning including etching process.
In this paper, we develop new RET and simultaneous patterning of Shallow Trench Isolation(STI) with gate
pattern which is using oxidation process of silicone. When we use nitride hard mask process and etching with this
oxidation process, we observed to achieve small resolution. Also we investigate process capability of this new process in
terms of CD control, STI height and so on.
Flexible electrode is essential for longitudinal or traverse type of micro-actuator using electrostrictive(ES) polymer. In this paper, two types of flexible electrode using conductive polymer(CP), carbon black composite and polypyrrole(PPy), was developed for a membrane type and unimorph type ES actuator using PU. At first, electrode using carbon black powder mixed with water-dispersed polyurethane was made and its displacement and dynamic characteristics were measured and compared with commercial conductive grease. Water-dispersed PU was produced by modified acetone process, using methylethylketone and acetone as solvent via NCO-terminated prepolymer. PU actuator was manufactured by stacking carbon black electrode(CBE) at both sides of half cured PU film with spin coater. Compared with conductive grease, displacement using carbon black electrode is approximately 60%. It can be thought that CBE has considerably more viscosity and less conductivity than conductive grease. Although PPy can be made from tens of nanometer to tens of micrometer thickness, phase shift occurs between PU film and PPy because of high temperature CVD process. It is estimated that high surface energy and low surface quality disturbs contacts with PU film.