With multi patterning being the method of choice for pushing technology further down the shrink roadmap, new design weak points are emerging that have multi-layer components and are difficult to find and to define. On the other hand, advanced OPC methodologies like retargeting and recentering help alleviate many of the occurrences, leaving only a few locations that are critical and need to be dealt with in design. State of the art in-design weak point auto fixing is usually done by identifying a weak point by a pattern match, and providing the router either a “safe” alternative configuration or tell it to reroute locally, also called rip-and-reroute. The dilemma for developing pattern matching decks that are used in place and route tools is that one cannot be too specific in the pattern definition as there will be escapes that can possibly cause problems in the fab. Having a more general pattern definition will prevent escapes, but will flag many locations that don’t really require fixing. As a consequence, this more general pattern definition may bog down the place and route tool and can actually result in area bloat if too many rip-and-reroute areas are identified. We have come up with a patented flow that allows very specific weak point detection with a low escape rate. The flow starts with a generic pattern definition of the fail mode, but reduces the number of occurrences by identifying safe configurations. Usually, the pattern extent of the safe configuration is larger than the initial generic pattern, and may contain more layers. Any known safe configuration is added to a “good pattern” database which is then subtracted from the initial pattern match. Thus, the number of design locations that need to be auto fixed is kept at a minimum. As the technology matures, more safe patterns are found and added to the database, thus reducing the amount of auto fixing required.
Via failure has always been a significant yield detractor caused by random and systematic defects. Introducing redundant vias or via bars into the design can alleviate the problem significantly [1] and has, therefore, become a standard DFM procedure [2]. Applying rule-based via bar insertion to convert millions of via squares to via bar rectangles, in all possible places where enough room could be predicted, is an efficient methodology to maximize the redundancy rate. However, inserting via bars can result in lithography hotspots. A Pattern Manufacturability (PATMAN) model is proposed, to maximize the Redundant Via Insertion (RVI) rate in a reasonable runtime, while insuring lithography friendly insertion based on the accumulated DFM learnings during the yield ramp.
Lithography process variation as well as etch and topography have always been a stubborn challenge for advanced technology nodes, i.e. 14nm and beyond. This variability usually results in defects aggregating around the edge of the wafer and leading to yield loss. A very tight process control is the logical resolution for such issues, nevertheless it might not be possible, or it may slow down the whole design to silicon cycle time. Another degree of difficulty is detecting these defects in ORC and concluding an OPC fix. In this paper, we show that aerial image ORC checks could provide a very useful insight to these defects ahead of time, and that they correlate well with silicon defects highlighted by CFM scan. This early detection upstream enables us to conclude a generic OPC fix for such issues and also improves the total OPC process-window enhancement and eliminates these defects on silicon.
At advanced technology nodes (sub-22 nm), design rules become very complicated as interactions between multiple layers become more complex, while the number of design elements within the optical radius increases. As a result, one may possibly encounter novel yield limiters in the 2D/3D design space with every new product taping out to the fab. Key to fast yield ramp is identifying novel constructs that may become yield detractors, and to address the challenge in the DFM space before actual Silicon is run. A comprehensive methodology to find such geometric constructs is proposed.
Proc. SPIE. 9427, Design-Process-Technology Co-optimization for Manufacturability IX
KEYWORDS: Data mining, Statistical analysis, Data modeling, Visualization, Data storage, Databases, Metals, Data processing, Profiling, Very large scale integration
Traditional physical design verification tools employ a deck of known design rules, each of which has a pre-defined pass/fail criteria associated with it. While passing a design rule deck is a necessary condition for a VLSI design to be manufacturable, it is not sufficient. Other physical design profiling decks that attempt to obtain statistical information about the various critical dimensions in the VLSI design lack a systematic methodology for rule enumeration. These decks are often inadequate, unable to extract all the interlayer and intralayer dimensions in a design that have a correlation with process yield. The Physical Design Analyzer is a comprehensive design analysis tool built with the objective of exhaustively exploring design-process correlations to increase the wafer yield.
Optical Proximity Correction (OPC) is a compute-intensive process used to generate photolithography mask shapes at advanced VLSI nodes. Previously, we reported a modified two-step OPC flow which consists of a first pattern replacement step followed by a model based OPC correction step [1]. We build on this previous work and show how this hybrid flow not only improves full chip OPC runtime, but also significantly improves mask correction consistency and overall mask quality. This is demonstrated using a design from the 20nm node, which requires the use of model based SRAF followed by model based OPC to obtain the full mask solution.
Techniques to control Across Chip CD Variation are very important in IC design, since it directly impacts the electrical timing and
functionality of the designs. VLSI designs today include a rich variety of electrical devices (different gate oxide thicknesses, different
threshold voltages, etc.) to provide the much needed flexibility to the chip designer. These devices occur at different proximities and
different densities on a full chip design. In this paper, we describe a method for improving and ensuring design-to-mask (D2M) quality
via a quantitative relationship between design specification and full chip tapeout results. This is done by applying a layout profiling
technique with the aim of capturing comprehensive representation of the design space, this method ensures the quality of design-to-mask
flow prior to release OPC data to mask house.
A methodology is described wherein a calibrated model-based ‘Virtual’ Variable Shaped Beam (VSB) mask writer
process simulator is used to accurately verify complex Optical Proximity Correction (OPC) and Inverse Lithography
Technology (ILT) mask designs prior to Mask Data Preparation (MDP) and mask fabrication. This type of
verification addresses physical effects which occur in mask writing that may impact lithographic printing fidelity
and variability. The work described here is motivated by requirements for extreme accuracy and control of
variations for today’s most demanding IC products. These extreme demands necessitate careful and detailed
analysis of all potential sources of uncompensated error or variation and extreme control of these at each stage of
the integrated OPC/ MDP/ Mask/ silicon lithography flow. The important potential sources of variation we focus on
here originate on the basis of VSB mask writer physics and other errors inherent in the mask writing process. The
deposited electron beam dose distribution may be examined in a manner similar to optical lithography aerial image
analysis and image edge log-slope analysis. This approach enables one to catch, grade, and mitigate problems early
and thus reduce the likelihood for costly long-loop iterations between OPC, MDP, and wafer fabrication flows. It
moreover describes how to detect regions of a layout or mask where hotspots may occur or where the robustness to
intrinsic variations may be improved by modification to the OPC, choice of mask technology, or by judicious design
of VSB shots and dose assignment.
Full chip model based Optical Proximity Correction (OPC) at
advanced nodes involves iteratively modifying the drawn polygon shapes
while simulating them through complex optical and resist models. Due to
the computational complexity of the models and the large size of VLSI
designs, these mask simulations run for very long times. In this study we
propose a pattern replacement step to generate a partial mask solution
before applying model based OPC correction. Since the pattern replacement
step is very fast and model based OPC has to be applied only to a
portion of the design, total mask generation runtime is significantly reduced.
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