Dr. Fedor G. Pikus Profile

Dr. Fedor G. Pikus

at Siemens EDA

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Author

Publications (12)

Proceedings Article | 28 March 2014 Paper

Work smarter not harder: How to get more results with less modeling

Kareem Madkour, Fedor Pikus, Mohab Anis

Proceedings Volume 9053, 905311 (2014) https://doi.org/10.1117/12.2046086

KEYWORDS: Transistors, Lithography, Model-based design, Resolution enhancement technologies, Performance modeling, Design for manufacturing, Optical proximity correction, Instrument modeling, Manufacturing, Statistical analysis

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Proceedings Article | 5 April 2011 Paper

Efficient approach to early detection of lithographic hotspots using machine learning systems and pattern matching

Jen-Yi Wuu, Fedor Pikus, Malgorzata Marek-Sadowska

Proceedings Volume 7974, 79740U (2011) https://doi.org/10.1117/12.879546

KEYWORDS: Machine learning, Lithography, Databases, Image classification, Phase modulation, Calibration, Manufacturing, Tolerancing, Design for manufacturability, Detection and tracking algorithms

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Proceedings Article | 23 September 2009 Paper

Challenges for the 28nm half node: Is the optical shrink dead?

J. Andres Torres, Oberdan Otto, Fedor Pikus

Proceedings Volume 7488, 74882A (2009) https://doi.org/10.1117/12.831047

KEYWORDS: Modulation transfer functions, Resolution enhancement technologies, Diffraction, Optical proximity correction, Chemical elements, Source mask optimization, Extreme ultraviolet, Process control, Coherence (optics), Image resolution

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A half-node process has been routinely used to deliver incremental improvements in process control and hardware availability in order to continue Moore's Law. Traditionally, due to the imaging requirements, parameters such as numerical aperture and partial coherence were not set to their maximum resolution settings, thus leaving room in hardware and RET recipes to accommodate incremental imaging requirements. However, as hardware availability and computational lithography methods are stressed to the maximum of their capabilities to deliver the next technology nodes, it is worth asking the question if such optical shrinks continue to be viable moving forward. Already 28nm layouts scaled down from the original 32nm layouts are starting to show signs of configuration limitations dictated by the available imaging hardware. In this paper we show that two-dimensional features determine the feasibility of migrating successfully to the next halfnode even when one-dimensional metrics suggest that such migration should be possible. While it has been proposed that methodologies that are based on fabrics can guarantee composability and are intrinsically easier to migrate to smaller nodes, such approaches are mostly valid for processes in which the frequency distribution of the object to be imaged remains compatible with the hardware and RET of choice. This paper suggests that the distribution and extent of the layout fabric discontinuities present one of the major hurdles to composability. In other words, it is not only necessary to determine the best pitch and width of the underlying fabric it becomes crucial to determine the distribution of the discontinuities present in the layout to build discrete devices. Given that the feasibility of a half-node process is determined mostly by its ability to achieve denser patterns without non-trivial layout modifications, in this paper we show that it is important to start looking at the explicit layout configuration aspects that determine layout printability. We have selected a pair of prototypical layout configurations common across all technology nodes of interest and have determined their intrinsic failure conditions for a given process. The results indicate that for a well padded 32nm process it may still be possible to perform an optical 28nm shrink with only a minimum of manual intervention, assuming that certain layout configurations are removed or carefully monitored during production. However, the nature of the analysis suggest that moving forward to 22nm and in the absence of higher-resolution hardware (i.e. EUV) optical shrinks that require little or no layout modifications to the desired patterns to be printed may no longer be possible.

Proceedings Article | 13 March 2009 Paper

Detecting context sensitive hot spots in standard cell libraries

Jen-Yi Wuu, Fedor Pikus, Andres Torres, Malgorzata Marek-Sadowska

Proceedings Volume 7275, 727515 (2009) https://doi.org/10.1117/12.814316

KEYWORDS: Lithography, Computer programming, Data modeling, Optics manufacturing, Resolution enhancement technologies, Manufacturing, Model-based design, Library classification systems, Visualization, Optical lithography

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Proceedings Article | 13 March 2009 Paper

Full flow for transistor simulation based on edge-contour extraction and advanced SPICE simulation

Eitan Shauly, Andres Torres, Loran Friedrich, Moran Cohen-Yasour, Ovadya Menadeva, Fedor Pikus

Proceedings Volume 7275, 727519 (2009) https://doi.org/10.1117/12.814361

KEYWORDS: Transistors, Device simulation, Calibration, Semiconducting wafers, Ions, Instrument modeling, Data modeling, Process modeling, Manufacturing, Electrochemical etching

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Proceedings Article | 13 March 2009 Paper

Circuit-topology driven OPC for increased performance/yield ratio

Edmund Pierzchala, Fedor Pikus, J. Andres Torres

Proceedings Volume 7275, 72751A (2009) https://doi.org/10.1117/12.814367

KEYWORDS: Optical proximity correction, Manufacturing, Clocks, Critical dimension metrology, Ions, Picosecond phenomena, Design for manufacturing, Digital electronics, Yield improvement, Logic

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Proceedings Article | 17 October 2008 Paper

Fast and simple modeling of non-rectangular transistors

Jen-Yi Wuu, Fedor Pikus, Malgorzata Marek-Sadowska

Proceedings Volume 7122, 71223S (2008) https://doi.org/10.1117/12.801541

KEYWORDS: Instrument modeling, TCAD, Device simulation, Transistors, Ions, Resolution enhancement technologies, Data modeling, Silicon, Process modeling, Computer simulations

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Proceedings Article | 17 October 2008 Paper

Non-uniform yield optimization for integrated circuit layout considering global interactions

J. Andres Torres, Fedor Pikus

Proceedings Volume 7122, 71223R (2008) https://doi.org/10.1117/12.801144

KEYWORDS: Design for manufacturing, Manufacturing, Photoresist processing, Yield improvement, Integrated circuits, Metals, Lithography, Visualization, Optimization (mathematics), Design for manufacturability

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Proceedings Article | 30 October 2007 Paper

Non-uniform yield optimization for integrated circuit layout

Fedor Pikus, J. Andres Torres

Proceedings Volume 6730, 67300Y (2007) https://doi.org/10.1117/12.746722

KEYWORDS: Design for manufacturing, Lithography, Failure analysis, Yield improvement, Composites, Manufacturing, Metals, Particles, Chemical mechanical planarization, Materials processing

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Proceedings Article | 21 March 2007 Paper

Unified process-aware system for circuit layout verification

J. Andres Torres, Fedor Pikus

Proceedings Volume 6521, 652108 (2007) https://doi.org/10.1117/12.711619

KEYWORDS: Design for manufacturing, Manufacturing, Lithography, Failure analysis, Metals, Composites, Resolution enhancement technologies, Data processing, Statistical analysis, Design for manufacturability

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Proceedings Article | 20 October 2006 Paper

Integrated DFM framework for dynamic yield optimization

Fedor Pikus

Proceedings Volume 6349, 63490F (2006) https://doi.org/10.1117/12.686440

KEYWORDS: Design for manufacturing, Yield improvement, Manufacturing, Photomask technology, Statistical analysis, Optical resolution, Resolution enhancement technologies, Optical proximity correction, Design for manufacturability

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Proceedings Article | 11 May 1994 Paper

Study of the mechanism of the heavy- and light-hole mixing in GaAs/AlAs superlattices by the exciton magnetoluminescence

G. Pikus, F. Pikus

Proceedings Volume 2139, (1994) https://doi.org/10.1117/12.175729

KEYWORDS: Excitons, Magnetism, Luminescence, Superlattices, Electrons, Interfaces, Polarization, Gallium arsenide, Active optics, Magnetic sensors

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Showing 5 of 12 publications

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