Quality of a layout has the most direct impact in the manufacturability of a design. Traditionally, layout quality is ensured in the first order by design rules, i.e. if a layout is free of design rules violation, it is a good layout. It is assumed such a layout will be fabricated to specification. Moreover, a design rule clean layout also ensures the electrical performance of the circuit it represents. There are other layout quality measures, e.g. random defects yield of a layout is modeled by critical area, systematic defects yield is sometime measured by a weighted score of recommended design rules. All the traditional layout quality measures are computed with drawn layout shapes.
In the advent of low K1 lithography and the increasing variability of process technologies beyond 90nm, nominal layout quality measures need to be revisited. Traditionally, nominal electrical properties such as L-eff and W-eff are extracted from drawn layout, and the corner cases are estimated with worst case process conditions. Most of these parameters are layout pattern dependent. As a matter of fact, they can be systematic through process and can have large impact in the modeling of circuit parameters .
In this paper, we investigate a through process layout quality measure, in which we extract through process electrical parameters from simulated through process resist contours. We showed a mechanism to compute a statistical model that predicts through process electrical parameters from the process parameter variation. We demonstrated that such computation is practical.
Tight ACLV control has become increasingly diffcult due to the diminishing process constant, K1. Focus variation and pitch variation are two major systematic components of ACLV. In this paper, we demonstrate these systematic effects and propose a design flow which exploits the systematic effect. We demonstrate the systematic ACLV by showing a Bossung plot for a nominal 90nm technology node. The plot is generated by simulation with lithographic parameters closely resembling a production technology node. Traditionally, tight CD control is achieved by sophisticated RET such as OPC, SRAF, AltPSM and more recently the Dense Template Design. The CD variation is specified in the design manual and the circuit designs will ensure functionality by building in enough margin to account for the variability. Even though, the systematic components of CD variation are understood, they have always been considered together with other
random components as being random. This approach has left design performance on the table. We propose a holistic design flow by integrating the technology development process, design process and the
manufacturing process. This holistic approach is aiming to tame the systematic through-pitch and through-focus CD variation. We quantify the design timing benefit using this approach by circuit design experiments. Results of our experiments show that timing uncertainty can be reduced by up to 30%. We also discuss other possibilities which are infeasible to carry out in traditional approach with silos of technology development, design and manufacturing.
One of the most compute intensive dataprep operations for 90nm PC level is the model-based optical proximity correction (MBOPC). The running time and output data size are growing unacceptably, particularly for ASICs and designs containing large macros built out of library cells (books). The reason for this growth is that the region-of-interest for MBOPC is approximately 600nm, which means that most library cells “see” interactions with adjacent books in the same row and also in adjacent rows.
In this paper, we investigate the merits of doing cellwise MBOPC. In its simplest form, the approach is to perform dataprep for each cell once per cell definition rather than once per placement. By inspection, this will reduce the computation time and output data size by a factor of P/D, where P is the number of book placements (100s to millions) and D is the number of book definitions.
Our preliminary finding indicates that there is negligible difference between nominal CD for cellwise corrected cells and chipwise corrected cells. We will present our finding in terms of average CD and contact coverage, as well as runtime reduction.
The likely possibility of having to support the 70 nm technology node with 193 nm lithography is lithography. The extremely significant resolution challenges and the ability of strong resolution enhancement techniques (RET) to meet them, is discussed. Evidence is presented that all strong RET impact the design flow by imposing nontrivial design restrictions. Data from an in-depth alternating phase shifted mask design feasibility assessment, conducted on the poly-gate level of the 180 nm technology node, is presented to give an outlook on the feasibility of RET-enabled design flows. Anticipated complications in taking such RET-enabled design flows to the complexity required for multiple critical levels of the 70nm node are discussed. An EDA solution focusing on complete integration of RET layout manipulations into the design flow is contrasted to an approach focusing on complex, optimized design rule comprises.
The International Technology Roadmap for Semiconductors lists F2 (157 nm exposure wavelength) optical lithography and extreme ultraviolet (EUV) next generation lithography as the two most feasible lithography solutions for the 70 nm technology node. It is very likely that both of these lithography solutions will be late, forcing ArF (193 nm exposure wavelength) lithography to operate at unprecedented resolution levels. Lithographically, alternating phase shifted masks (altPSM) can achieve the resolution required to manufacture 70 nm logic products with ArF lithography equipment [P. Schiavone, F. Lalanne, and A. Prola, "Clear field alternating PSM for 193 nm lithography," Proc. SPIE 3679, 582-589 (1999) and M. Fritz et al., "Application of chromeless phase-shift masks to sub-100 nm SOI CMOS transistor fabrication," Proc. SPIE 4000, 388-407 (2000)], but technical and logistical challenges associated with the broad implementation of altPSM require novel and invasive EDA solutions which have caused the industry to shy away from altPSM in the past. Since the resolution capabilities of altPSM are well understood in the lithography community, this paper will focus on the challenges facing altPSM implementation for the polysilicon gate level and will present the results of a detailed altPSM design feasibility study done at IBM for the 180 nm technology node. While the 70 nm technology node will push resolution harder then ever before, the design rules, EDA tools, and layout methodologies developed in the past lay the foundation for our attack on this challenging technology node.
SC889: Layout-Aware Circuit Analysis
This course is directed towards presenting a methodology to include layout effects on circuit analysis. DFM imposes embellishments on the layout to ensure manufacturability with acceptable yields. Traditional circuit analysis and effects of process variability are performed at the schematics level using models for process corners and may lead to excessive guardbanding. Circuit Analysis that is able to predict impact and sensitivity of layout modifications uses circuit simulators together with information derived from litho simulations and helps the designer to ascertain that the layout accompanying the design meets the manufacturability criteria.
Sub-90nm CMOS technologies are giving rise to significant variation in physical parameters of VLSI designs which has adverse impact on their electrical behavior. Most manufacturing-oriented professionals are familiar with the variations in physical parameters. This course will provide attendees with knowledge of how these physical variations impact the circuit operations, i.e., their electrical behavior. The impact on timing as well as power will be discussed. We will describe relative impact of these variations on various circuit families as well as circuit design techniques to mitigate the impact of manufacturing variations. Due to the large mangnitude of these variations, it is clear that designing for worst case behavior leaves significant performance on the table. We will discuss how systematic variation can be exploited in the current static timing methodology if it is known. A statistical timing and design methodology will also be discussed that can help regain some of this performance. With an eye towards the future, we will also explore manufacturing aware design closure. The course will be illustrated with practical examples throughout.