Although lens aberrations in EUV imaging systems are very small, aberration impacts on pattern placement error and overlay error need to be carefully investigated to obtain the most robust lithography process for high volume manufacturing. Instead of focusing entirely on pattern placement errors in the context of a single lithographic process, we holistically study the interaction between two sequential lithographic layers affected by evolving aberration wavefronts, calculate aberration induced overlay error, and explore new strategies to improve overlay.
Pellicles that satisfy transmission, emission, thermal, and mechanical requirements are highly desired for EUV high volume manufacturing. We present here the capability of integrating pellicles in the full flow of rigorous EUV lithography simulations. This platform allows us to investigate new coherence effects in EUV lithography when pellicle is used. Critical dimension uniformity and throughput loss due to pellicle defects and add-on particles are also analyzed. Our study provides theoretical insights into pellicle development and facilitates pellicle insertion in EUV lithography.
The initial readiness of EUV patterning was demonstrated in 2016 with IBM Alliance's 7nm device
technology. The focus has now shifted to driving the 'effective' k1 factor and enabling the second
generation of EUV patterning. Thus, Design Technology Co-optimization (DTCO) has become a critical
part of technology enablement as scaling has become more challenging and the industry pushes the limits
of EUV lithography. The working partnership between the design teams and the process development
teams typically involves an iterative approach to evaluate the manufacturability of proposed designs,
subsequent modifications to those designs and finally a design manual for the technology. While this
approach has served the industry well for many generations, the challenges at the Beyond 7nm node require
a more efficient approach. In this work, we describe the use of “Design Intent” lithographic layout
optimization where we remove the iterative component of DTCO and replace it with an optimization that
achieves both a “patterning friendly” design and minimizes the well-known EUV stochastic effects.
Solved together, this “design intent” approach can more quickly achieve superior lithographic results while
still meeting the original device’s functional specifications.
Specifically, in this work we will demonstrate “design intent” optimization for critical BEOL layers using
design tolerance bands to guide the source mask co-optimization. The design tolerance bands can be either
supplied as part of the original design or derived from some basic rules. Additionally, the EUV stochastic
behavior is mitigated by enhancing the image log slope (ILS) for specific key features as part of the overall
optimization. We will show the benefit of the “design intent approach” on both bidirectional and
unidirectional 28nm min pitch standard logic layouts and compare the more typical iterative SMO
approach. Thus demonstrating the benefit of allowing the design to float within the specified range.
Lastly, we discuss how the evolution of this approach could lead to layout optimization based entirely on
some minimal set of functional requirements and process constraints.
Optical metrology tool, LX530, is designed for high throughput and dense sampling metrology in semiconductor manufacture. It can inspect the dose and focus variation in the process control based on the critical dimension (CD) and line edge roughness (LER) measurement. The working principle is shown with a finite-difference-time-domain (FDTD) CD simulation. Two optical post lithography wafers, including one focus-exposure-matrix (FEM) wafer and one nominal wafer, are inspected for CD, dose and focus analysis. It is demonstrated that dose and focus can be measured independently. A data output method based on global CD uniformity (CDU), inter CDU and intra CDU is proposed to avoid the data volume issue in dense sampling whole wafer inspection.
Unlike optical masks which are transmissive optical elements, use of extreme ultraviolet (EUV) radiation requires a reflective mask structure - a multi-layer coating consisting of alternating layers of high-Z (wave impedance) and low-Z materials that provide enhanced reflectivity over a narrow wavelength band peaked at the Bragg wavelength.1 Absorber side wall angle, corner rounding,2 surface roughness,3 and defects4 affect mask performance, but even seemingly simple parameters like bulk reflectivity on mirror and absorber surfaces can have a profound influence on imaging. For instance, using inaccurate reflectivity values at small and large incident angles would diminish the benefits of source mask co-optimization (SMO) and result in larger than expected pattern shifts.
The goal of our work is to calculate the variation in mask reflectivity due to various sources of inaccuracies using Monte Carlo simulations. Such calculation is necessary as small changes in the thickness and optical properties of the high-Z and low-Z materials can cause substantial variations in reflectivity. This is further complicated by undesirable intermixing between the two materials used to create the reflector.5 One of the key contributors to mask reflectivity fluctuation is identified to be the intermixing layer thickness. We also investigate the impacts on OPC when the wrong mask information is provided, and evaluate the deterioration of overlapping process window. For a hypothetical N7 via layer, the lack of accurate mask information costs 25% of the depth of focus at 5% exposure latitude. Our work would allow the determination of major contributors to mask reflectivity variation, drive experimental efforts of measuring such contributors, provide strategies to optimize mask reflectivity, and quantize the OPC errors due to imperfect mask modeling.
We report on the printability, mitigation and actinic mask level review of programmed substrate blank pit and bump defects in a EUV lithography test mask. We show the wafer printing behavior of these defects exposed with an NXE:3300 EUV lithography scanner and the corresponding mask level actinic review using the AIMSTM tool. We will show which categories of these blank substrate defects print on wafer and how they can be mitigated by hiding these defects under absorber lines. Furthermore we show that actinic AIMSTM mask review images of these defects, in combination with a simple thresholded resist transfer model, can accurately predict their wafer printing profiles. We also compare mask level actinic AIMSTM to top down mask SEM review in their ability to detect these defects.