Gaussian filtering is a basic tool for image processing. Noise reduction, scale-space generation or edge detection
are examples of tasks where different Gaussian filters can be successfully utilized. However, their implementation
in a conventional digital processor by applying a convolution kernel throughout the image is quite inefficient.
Not only the value of every single pixel is taken into consideration sucessively, but also contributions from their
neighbors need to be taken into account. Processing of the frame is serialized and memory access is intensive
and recurrent. The result is a low operation speed or, alternatively, a high power consumption. This inefficiency
is specially remarkable for filters with large variance, as the kernel size increases significantly. In this paper, a
different approach to achieve Gaussian filtering is proposed. It is oriented to applications with very low power
budgets. The key point is a reconfigurable focal-plane binning. Pixels are grouped according to the targeted
resolution by means of a division grid. Then, two consecutive shifts of this grid in opposite directions carry
out the spread of information to the neighborhood of each pixel in parallel. The outcome is equivalent to the
application of a 3×3 binomial filter kernel, which in turns is a good approximation of a Gaussian filter, on the
original image. The variance of the closest Gaussian filter is around 0.5. By repeating the operation, Gaussian
filters with larger variances can be achieved. A rough estimation of the necessary energy for each repetition until
reaching the desired filter is below 20nJ for a QCIF-size array. Finally, experimental results of a QCIF proofof-
concept focal-plane array manufactured in 0.35μm CMOS technology are presented. A maximum RMSE of
only 1.2% is obtained by the on-chip Gaussian filtering with respect to the corresponding equivalent ideal filter
Single-photon avalanche diodes are compatible with standard CMOS. It means that photo-multipliers for scintillation
detectors in nuclear medicine (i. e. PET, SPECT) can be built in inexpensive technologies. These
silicon photo-multipliers consist in arrays of, usually passively-quenched, SPADs whose output current is sensed
by some analog readout circuitry. In addition to the implementation of photosensors that are sensitive to singlephoton
events, analog, digital and mixed-signal processing circuitry can be included in the same CMOS chip.
For instance, the SPAD can be employed as an event detector, and with the help of some in-pixel circuitry, a
digitized photo-multiplier can be built in which every single-photon detection event is summed up by a counter.
Moreover, this concurrent processing circuitry can be employed to realize low level image processing tasks. They
can be efficiently implemented by this architecture given their intrinsic parallelism. Our proposal is to operate
onto the light-induced signal at the focal plane in order to obtain a more elaborated record of the detection.
For instance, by providing some characterization of the light spot. Information about the depth-of-interaction,
in scintillation detectors, can be derived from the position and shape of the scintillation light distribution. This
will ultimately have an impact on the spatial resolution that can be achieved. We are presenting the design in
CMOS of an array of detector cells. Each cell contains a SPAD, an MOS-based passive quenching circuit and
drivers for the column and row detection lines.