28nm metal 90nm pitch is one of the most challenging processes for computational lithography due to the resolution limit of DUV scanners and the variety of designs allowed by design rules. Classical two dimensional hotspot simulations and OPC correction isn’t sufficient to obtain required process windows for mass production. This paper shows how three dimensional resist effects like top loss and line end shortening have been calibrated and used during the OPC process in order to achieve larger process window. Yield results on 28FDSOI product have been used to benchmark and validate gain between classical OPC and R3D OPC.
The 2x nm generation of advanced designs presents a major lithography challenge to achieve adequate correction due to
the very low k1 values. The burden thus falls on resolution enhancement techniques (RET) in order to be able to achieve
enough image contrast, with much of this falling to computational lithography. Advanced mask correction techniques can
be computationally expensive. This paper presents a methodology that enables advanced mask quality with the cost of
much simpler methods. Brion Technologies has developed a product called Flexible Mask Optimization (FMO) which
identifies hotspots, applies an advanced technique to improve them, performs model based boundary healing to reinsert
the repaired hotspot cleanly (without introducing new hotspots), and then performs a final verification.
STMicroelectronics has partnered with Brion to evaluate and prove out the capability and performance of this approach.
The results shown demonstrate improved performance on 2x nm node complex 2D hole layers using a hybrid approach
of rule based sub resolution assist features (RB-SRAF) and model based SRAF (MB-SRAF). The effective outcome is to
achieve MB-SRAF levels of quality but at only a slightly higher computational cost than a quick, cheap rule based
As the OPC scripts become more and more complex for advanced technology nodes, the number of parameters
used to control the convergence increases drastically. This paper does not aim to determine what a "good
convergence criteria" is but rather to review the efficiency of the existing OPC solutions in terms of accuracy
and parameter dependence, to solve simple design layouts. Three different OPC solutions, including a "standard
algorithm", a "local convergence OPC" and a more holistic OPC, are compared on a design containing lines and
line-ends. A cost function is used to determine the quality of the convergence for each type of structure. A map
of convergence (iteration vs OPC Option) will be deduced for each structure.
For mature technology nodes, main yield detractor is random defectivity.
Nevertheless, some devices can show higher defectivity than rest of devices. Out of
process accident, design related defect is one of suspected root cause. Also, design-based
defect category is expected to increase as technology node decreases. Determining origin
of these additional systematic defects is not easy as these defects are usually residual for
technologies in production, not always predictable by OPC simulator (ex: void defect in
active STI structure), and at least hidden by random defectivity after in-line wafer
In this paper, an automatic flow to track systematic defects within global
defectivity is presented. This flow starts with a relevant selection of several inspection
defect files for a given device. Then the Design Based Binning (DBB) tool performs a
fine alignment of the whole multi wafer inspection data set with design file. The resulting
aligned defect file is treated by an efficient pattern matching algorithm to generate a
design-based binning (DBB) defect file. The integration of this output defect file into a
Yield Management System (YMS) allows easy defect analysis and statistical correlation to electrical results. An example of design-based defects tracking analysis and their impact on yield of a mature technology node device is presented in this paper.
Optical Proximity Correction (OPC) is used in lithography to increase the achievable resolution and pattern transfer
fidelity for IC manufacturing. Nowadays, immersion lithography scanners are reaching the limits of optical resolution
leading to more and more constraints on OPC models in terms of simulation reliability. The detection of outliers coming
from SEM measurements is key in OPC . Indeed, the model reliability is based in a large part on those measurements
accuracy and reliability as they belong to the set of data used to calibrate the model. Many approaches were developed
for outlier detection by studying the data and their residual errors, using linear or nonlinear regression and standard
deviation as a metric .
In this paper, we will present a statistical approach for detection of outlier measurements. This approach consists of
scanning Critical Dimension (CD) measurements by process conditions using a statistical method based on fuzzy CMean
clustering and the used of a covariant distance for checking aberrant values cluster by cluster. We propose to use
the Mahalanobis distance  in order to improve the discrimination of the outliers when quantifying the similarity within
each cluster of the data set.
This fuzzy classification method was applied on the SEM CD data collected for the Active layer of a 65 nm half pitch
technology. The measurements were acquired through a process window of 25 (dose, defocus) conditions. We were able
to detect automatically 15 potential outliers in a data distribution as large as 1500 different CD measurement. We will
discuss about these results as well as the advantages and drawbacks of this technique as automatic outliers detection for
large data distribution cleaning.
In advanced technology nodes, due to accuracy and computing time constraint, OPC has shifted from discrete simulation
to pixel based simulation. The simulation is grid based and then interpolation occurs between grid points. Even if the
sampling is done below Nyquist rate, interpolation can cause some variations for same polygon placed at different
location in the layout. Any variation is rounded during OPC treatment, because of discrete numbers used in OPC output
file. The end result is inconsistency in post-OPC layout, where the same input polygon will give different outputs,
depending on its position and orientation relative to the grid. This can have a major impact in CD control, in structures
like SRAM for example, where mismatching between gates can cause major issue.
There are some workarounds to minimize this effect, but most of them are post-treatment fix. In this paper, we will try to
identify and solve the root cause of the problem. We will study the relationship between the pixel size and the
consistency of post OPC results. The pixel size is often set based on optical parameters, but it might be possible to
optimize it around this value to avoid inconsistency. One can say that the optimization will highly depend on design and
not be possible for a real layout. As the range of pitch used in a design tends to decrease, thanks to fix pitch layouts, we
may optimize pixel size for a full layout.
In the continuous battle to improve critical dimension (CD) uniformity, especially for 45-nanometer (nm) logic
advanced products, one important recent advance is the ability to accurately predict the mask CD uniformity
contribution to the overall global wafer CD error budget. In most wafer process simulation models, mask error
contribution is embedded in the optical and/or resist models. We have separated the mask effects, however, by
creating a short-range mask process model (MPM) for each unique mask process and a long-range CD
uniformity mask bias map (MBM) for each individual mask. By establishing a mask bias map, we are able to
incorporate the mask CD uniformity signature into our modelling simulations and measure the effects on global
wafer CD uniformity and hotspots. We also have examined several ways of proving the efficiency of this
approach, including the analysis of OPC hot spot signatures with and without the mask bias map (see Figure 1)
and by comparing the precision of the model contour prediction to wafer SEM images. In this paper we will
show the different steps of mask bias map generation and use for advanced 45nm logic node layers, along with
the current results of this new dynamic application to improve hot spot verification through Brion Technologies'
model-based mask verification loop.
This paper present an evaluation of our CMOS 45nm gate patterning process performance based on immersion
lithography in a production environment. A CD budget breakdown is shown detailing lot to lot, wafer to wafer,
intrawafer, intrafield and proximity CD uniformity characterization. Emphasis is given on scatterometry library
development and deployment. We also look more into detail to focus effect on CD control. Finally status of overlay
performance with immersion lithography is also presented.
At 45 and 32 nm nodes, one of the most critical layers is the Contact one. Due to the use of hyper NA imaging, the
depth of focus starts to be very limited.
Moreover the OPC is rapidly limited because of the increase of the pattern density. The limited surface in the dark field
region of a Contact layer mask enforces the edges movement to stop very quickly.
The use of SRAF (Sub Resolution Assist Feature) has been widely use for DOF enhancement of line and space layers
since many technology node. Recently, SRAF generated using inverse lithography have shown interesting DOF
improvement1. However, the advantage of the ideal mask generated by inverse lithography is lost when switching to a
manufacturable mask with Manhattan structures. For SRAF placed in rule based as well as Manhattan SRAF generated
after inverse lithography, it is important to know what their behavior is, in term of size and placement.
In this article we propose to study the placement of scatter-trenches assist features for the contact layer. For this we have
performed process window simulation with different SRAF sizes and distance to the main OPC. These results permit us
to establish the trends for size and placement of the SRAF.
Moreover we have also take a look of the advantages of using 8 surrounding SRAF (4 in vertical - horizontal and 4 at
45°) versus 4 surrounding SRAF. Based on these studies we have seen that there is no real gain of increasing the
complexity by adding additional SRAF.
The perpetual shrinking in critical dimensions in semiconductor devices is driving the need for increased resolution in optical lithography. Increasing NA to gain resolution also increases Optical Proximity Correction (OPC) model complexity. Some optical effects which have been completely neglected in OPC modeling become important. Over the past few years, off-axis illumination has been widely used to improve the imaging process. OPC models which utilize such illumination still use the thin film mask approximation (Kirchhoff approach), during optical model generation, which utilizes a normal incidence. However, simulating a three dimensional mask near-field using an off-axis illumination requires OPC models to introduce oblique incidence. In addition, the use of higher NA systems introduces high obliquity field components that can no longer be assimilated as normal incident waves. The introduction of oblique incidence requires other effects, such as corner rounding of mask features, to be considered, that are seldom taken into account in OPC modeling. In this paper, the effects of oblique incidence and corner rounding of mask features on resist contours of 2D structures (i.e. line-ends and corners) are studied. Rigorous electromagnetic simulations are performed to investigate the scattering properties of various lithographic 32nm node mask structures. Simulations are conducted using a three dimensional phase shift mask topology and an off-axis illumination at high NA. Aerial images are calculated and compared with those obtained from a classical normal incidence illumination. The benefits of using an oblique incidence to improve hot-spot prediction will be discussed.
One of the most critical points for accurate OPC is to have accurate models that properly simulate the full process from
the mask fractured data to the etched remaining structures on the wafer. In advanced technology nodes, the CD error
budget becomes so tight that it is becoming critical to improve modeling accuracy. Current technology models used for
OPC generation and verification are mostly composed of an optical model, a resist model and sometimes an etch model.
The mask contribution is nominally accounted for in the optical and resist portions of these models. Mask processing
has become ever more complex throughout the years so properly modeling this portion of the process has the potential
to improve the overall modeling accuracy. Also, measuring and tracking individual mask parameters such as CD bias
can potentially improve wafer yields by detecting hotspots caused by individual mask characteristics. In this paper, we
will show results of a new approach that incorporates mask process modeling. We will also show results of testing a
new dynamic mask bias application used during OPC verification.
Patterning isolated trenches for bright field layers such as the active layer has always been difficult for lithographers.
This patterning is even more challenging for advanced technologies such as the 45-nm node where most of the process
optimization is done for minimum pitch dense lines.
Similar to the use of scattering-bars to assist isolated lines structures, we can use inverse Sub Resolution Assist Features
(SRAF) to assist the patterning of isolated trenches structures.
Full characterization studies on the C45 Active layer demonstrate the benefits and potential issues of this technique: Screen Inverse SRAF parameters (size, distance to main feature) utilizing optical simulation; Verify simulation predictions and ensure sufficient improvement in Depth of Focus and Exposure latitude with
silicon process window analysis; Define Inverse SRAF OPC generation script parameters and validate, with accurate on silicon, measurement
characterization of specific test patterns; Maskshop manufacturability through CD measurements and inspection capability.
Finally, initial silicon results from a 45nm mask are given with suggestions for additional optimization of inverse SRAF
Several qualification stages are required for new maskshop tools, first step is done by the maskshop internally. Taking
a new writer for example, the maskshop will review the basic factory and site acceptance tests, including CD
uniformity, CD linearity, local CD errors and registration errors. The second step is to have dedicated OPC (Optical
Proximity Correction) structures from the wafer fab. These dedicated OPC structures will be measured by the
maskshop to get a reticle CD metrology trend line.
With this trend line, we can:
- ensure the stability at reticle level of the maskshop processes
- put in place a matching procedure to guarantee the same OPC signature at reticle level in case of any
internal maskshop process change or new maskshop evaluation. Changes that require qualification could
be process changes for capacity reasons, like introducing a new writer or a new manufacturing line, or for
capability reasons, like a new process (new developer tool for example) introduction.
Most advanced levels will have dedicated OPC structures. Also dedicated maskshop processes will be monitored with
these specific OPC structures.
In this paper, we will follow in detail the different reticle CD measurements of dedicated OPC structures for the three
advanced logic levels of the 65nm node: poly level, contact level and metal level. The related maskshop's processes are
- for poly: eaPSM 193nm with a nega CAR (Chemically Amplified Resist) process for Clear Field L/S
(Lines & Space) reticles
- for contact: eaPSM 193nm with a posi CAR process for Dark Field Holes reticles
- for metal1: eaPSM 193nm with a posi CAR process for Dark Field L/S reticles.
For all these structures, CD linearity, CD through pitch, length effects, and pattern density effects will be monitored.
To average the metrology errors, the structures are placed twice on the reticle.
The first part of this paper will describe the different OPC structures. These OPC structures are close to the DRM
(Design Rule Manual) of the dedicated levels to be monitored.
The second part of the paper will describe the matching procedure to ensure the same OPC signature at reticle level.
We will give an example of an internal maskshop matching exercise, which could be needed when we switched from
an already qualified 50 KeV tool to a new 50 KeV tool.
The second example is the same matching exercise of our 65nm OPC structures, but with two different maskshops.
The last part of the paper will show first results on dedicated OPC structures for the 45nm node.
As semiconductor technology moves toward and beyond the 65 nm lithography node, the importance of Optical
Proximity Correction (OPC) models grows due to the lithographer's need to ensure high fidelity in the mask-
to-silicon transfer. This, in turn, causes OPC model complexity to increase as NA increases and minimum
feature size on the mask decreases. Subtle effects, that were considered insignificant, can no longer be ignored.
Depending on the imaging system, three dimensional mask effects need to be included in OPC modeling. These
effects can be used to improve model accuracy and to better predict the final process window. In this paper,
the effects of 3D mask topology on process window are studied using several 45 nm node mask structure types.
Simulations are conducted with and without a polarized illumination source. The benefits of using an advanced model algorithm, that comprehends 3D mask effects, will be discussed. To quantify the potential impact of this methodology, relative to current best known practices, all results are compared to those obtained from a model using a conventional thin film mask.
The quality of model-based OPC correction depends strongly on how the model is calibrated in order to generate a resist image as close to the desired shapes as possible. As the k1 process factor decreases and design complexity increases, the correction accuracy and the model stability become more important. It is also assumed that the stability of one model can be tested when its response to a small variation in one or several parameters is small. In order to quantify this, the small-variation method has been tested on a variable threshold based model initially optimized for the 65nm node using measurements done with a test pattern mask. This method consists of introducing small variations to one input model parameter and analyzing the induced effects on the simulated edge placement error (EPE). In this paper, we study the impact of small changes in the optical and resist parameters (focus settings, inner and outer partial coherent factors, NA, resist thickness) on the model stability. And then, we quantify the sensitivity of the model towards each parameter shift. We also study the effects of modeling parameters (kernel count, model fitness, optical diameter) on the resulting simulated EPE. This kind of study allows us to detect coverage or process window problems. The process and modeling parameters have been modified one by one. The ranges of variations correspond to those observed during a typical experiment. Then the difference in simulated EPE between the reference model and the modified one has been calculated. Simulations show that the loss in model accuracy is essentially caused by changes in focus, outer sigma and NA and lower values of optical diameter and kernel count. Model results agree well with a production layout.
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must guarantee high imaging fidelity throughout the entire range of normal process variations. To verify the printability of a design across process window, compact optical models similar to those used for standard OPC are used. These models are calibrated from experimental data measured at the limits of the process window. They are then applied to the design to predict potential printing failures. This approach has been widely used for dry lithography. With the emergence of immersion lithography in production in the IC industry, the predictability of this approach has to be validated on this new lithographic process. In this paper, a comparison between the dry lithography process model and the immersion lithography process model is presented for the Poly layer at 65 nm node patterning. Examples of specific failure predictions obtained separately with the two processes are compared with experimental results. A comparison in terms of process performance will also be a part of this study.
Ensuring robust patterning after OPC is becoming more and more difficult due to the continuous reduction of layout
dimensions and diminishing process windows associated with each successive lithographic generation. Lithographers must
guarantee high imaging fidelity throughout the entire range of normal process variations. As a result, post-OPC verification
methods have become indispensable tools for avoiding pattern printing issues. The majority of these methods are primarily
based on lithographic simulations of pattern printing behaviour across dose and focus variations. The models used for these
simulations are compact optical models combined with one single resist model. Even if very predictive resist models exist,
they have often a large number of parameters to fit and suffer from long computing times to execute the simulations.
Simplified resist models are thus needed to enhance run-time computing during simulation.
The objective of this study is to test the predictability of such resist models across the process window. Two
different resist models will be considered in this study. The first resist model is a pure variable threshold resist model. The
second resist modelling approach is a simplified physical model which uses Gaussian convolutions and a constant threshold
to model resist printing behaviour. The study concentrates on poly layer patterning for the 65 nm node. Examples of specific
simulations obtained with the two different techniques are compared against experimental results.
The 65nm and 45nm device generations will be used to manufacture large designs using complex patterning processes in combination with exotic model-based or rule-based RETs’ scenarios. The lithography for these generations will operate in the low k1 regime value resulting in small process window and tight overlay requirements. Therefore, the potential for having yield limiting errors due to RET-process-design interactions is significantly higher than with the 130nm generation.
Additionally, the high cost of reticles and the large number of process layers make it quite important to catch these costly errors.
Optical Rule Checking (ORC) is an effective way to predict failure on wafer shapes. Used in addition to Optical Proximity Correction, it can help to reduce failures affecting yield in manufacturing. Thus, due to the inter-layer complexity of processes and RET, the necessity to check accurately particular areas which could generate costly errors is growing:
Here are some examples: 1) Low metal-contact or metal-via overlaps, 2) Small poly extension past active area, 3) Low overlap between poly and contact layers, and 4) Dual exposure techniques for single layer patterning.
The main difficulty in current implementation of multiple layer RET verification is the trade off between accuracy vs. runtime vs. fault coverage.
In this paper we will demonstrate how based on this trade off we can enhance our final printed results by accurately targeting the most likely failure mechanism on multiple layer processes check in a production environment (90nm node product layout). Finally we will show how ORC in a multiple layer check is going to help detect faults and overlay sensitive areas so as to secure process weakness areas.
We will compare several softwares where such a methodology is applied and attend to propose a post OPC verification strategy to obtain a more robust manufacturing process.
Specifications for CD control on current technology nodes have become very tight, especially for the gate level. Therefore all systematic errors during the patterning process should be corrected. For a long time, CD variations induced by any change in the local periodicity have been successfully addressed through model or/and rule based corrections. However, if long-range effects (stray light, etch, and mask writing process...) are often monitored, they are seldom taken into account in OPC flows.
For the purpose of our study, a test mask has been designed to measure these latter effects separating the contributions of three different process steps (mask writing, exposure and etch). The resulting induced CD errors for several patterns are compared to the allowed error budget. Then, a methodology, usable in standard OPC flows, is proposed to calculate the required correction for any feature in any layout. The accuracy of the method will be demonstrated through experimental results.
In the context of 65nm logic technology where gate CD control budget requirements are below 5nm, it is mandatory to properly quantify the impact of the 2D effects on the electrical behavior of the transistor [1,2]. This study uses the following sequence to estimate the impact on transistor performance:
1) A lithographic simulation is performed after OPC (Optical Proximity Correction) of active and poly using a calibrated model at best conditions. Some extrapolation of this model can also be used to assess marginalities due to process window (focus, dose, mask errors, and overlay). In our case study, we mainly checked the poly to active misalignment effects.
2) Electrical behavior of the transistor (Ion, Ioff, Vt) is calculated based on a derivative spice model using the simulated image of the gate as an input. In most of the cases Ion analysis, rather than Vt or leakage, gives sufficient information for patterning optimization. We have demonstrated the benefit of this approach with two different examples:
-design rule trade-off : we estimated the impact with and without misalignment of critical rules like poly corner to active distance, active corner to poly distance or minimum space between small transistor and big transistor.
-Library standard cell debugging: we applied this methodology to the most critical one hundred transistors of our standard cell libraries and calculate Ion behavior with and without misalignment between active and poly. We compared two scanner illumination modes and two OPC versions based on the behavior of the one hundred transistors. We were able to see the benefits of one illumination, and also the improvement in the OPC maturity.