Corner rounding improvement is critical to device performance, yield, and cell area reduction. In this paper, we present a method to use dual tone sub-resolution assist feature (SRAF) to improve both the outer corner rounding and inner corner rounding which in turn enhance the pattern quality. The simulation data and wafer data are presented. A few parameters have been investigated, such as the position of the SRAF, the shape of the SRAF, resist type and mask tone. The preliminary results show that more than 40% reduction of both inner corner rounding and outer corner rounding can be achieved by placing sub-resolution assist features at appropriate locations. The limit of corner rounding improvement is determined by mask rule check (MRC) and resist sensitivities.
This paper describes a rigorous yet flexible standard cell place-and-route flow that is used to quantify block-level power, performance, and area trade-offs driven by two unique cell architectures and their associated design rule differences. The two architectures examined in this paper differ primarily in their use of different power-distribution-networks to achieve the desired circuit performance for high-performance logic designs. The paper shows the importance of incorporating block-level routability experiments in the early phases of design-technology co-optimization by reviewing a series of routing trials that explore different aspects of the technology definition. Since the electrical and physical parameters leading to critical process assumptions and design rules are unique to specific integration schemes and design objectives, it is understood that the goal of this work is not to promote one cell-architecture over another, but rather to convey the importance of exploring critical trade-offs long before the process details of the technology node are finalized to a point where a process design kit can be published.
Line edge roughness (LER) reduction is critical during the patterning process definition and development, as the critical dimension (CD) and pitch scale in advanced semiconductor technology nodes. In this paper, we will focus on a 7nm self-aligned double patterning (SADP) process for use in back end of line (BEOL). Specifically, we will investigate LER from various lithography options and how LER changes through downstream processes, including mandrel etch, spacer deposition, hard mask open, dielectric etch and wet clean. We characterized LER as a function of several mandrel etch parameters such as O2 flow rate, over etch rate percentage and polymer deposition rates. We also characterized LER response to dielectric etch parameters and found that while some etch processes may smooth high frequency LER, there are additional cases where the final etch and wet-clean increased LER and line wiggling. Overall, we observed that lithography is the primary source of LER and we have the opportunity to reduce LER by both design and process optimization. In this paper we focused on characterization of a standard logic cell with varied CD and pitch. We looked through various designs, retargeting as well as both negative tone developer (NTD) and positive tone developer (PTD) resists for the LER reduction. We also analyzed the image log slope (ILS) of each corresponding edge and the process windows of the resist candidates. We concluded that ILS improvement and resist selection are the primary knobs to reduce LER. With optimization, we can achieve LER close to the process assumption targets for 7nm technology node. Further LER reduction techniques are definitely needed in both 7nm and future nodes even with migration from 193nm to EUV lithography.
Vote-taking lithography sums up N mask images, each at 1/N dose, to mitigate the mask defects on each individual mask. The fundamental assumption is that the mask defects do not correlate in position from mask to mask, and so each individual defect will be blended with good images from the other N-1 masks. This paper will explore vote-taking for EUV lithography with both simulation and experimental results. PROLITH simulations will show the size of defects that can be healed for different N, the number of masks. SEM images of NXE 3300 exposures will be shown that are similar to those predicted from simulation. The implementation of vote-taking lithography for High Volume Manufacturing has huge practical and economic barriers. Some expose tool capabilities that could enable vote-taking lithography will be discussed. Besides defect mitigation, we briefly speculate on other possible imaging benefits opened up by voting with several exposure passes.
The feature scaling and patterning control required for the 7nm node has introduced EUV as a candidate lithography technology for enablement. To be established as a front-up lithography solution for those requirements, all the associated aspects with yielding a technology are also in the process of being demonstrated, such as defectivity process window through patterning transfer and electrical yield. This paper will review the current status of those metrics for 7nm at IBM, but also focus on the challenges therein as the industry begins to look beyond 7nm. To address these challenges, some of the fundamental process aspects of holistic EUV patterning are explored and characterized. This includes detailing the contrast entitlement enabled by EUV, and subsequently characterizing state-of-the-art resist printing limits to realize that entitlement. Because of the small features being considered, the limits of film thinness need to be characterized, both for the resist and underlying SiARC or inorganic hardmask, and the subsequent defectivity, both of the native films and after pattern transfer. Also, as we prepare for the next node, multipatterning techniques will be validated in light of the above, in a way that employs the enabling aspects of EUV as well. This will thus demonstrate EUV not just as a technology that can print small features, but one where all aspects of the patterning are understood and enabling of a manufacturing-worthy technology.
This paper reviews the escalation in design constraints imposed on 2nd level wiring by multiple patterning exposure techniques in the 10NM technology node (i.e. ~45nm wiring pitch) relative to the 14NM technology node (i.e. 64nm wiring pitch). Specifically, new challenges facing place-and-route tooling are outlined, solutions to overcome these challenges are reviewed, and a manufacturing ready implementation is demonstrated.
We discuss the lithographic qualification of a new type of binary mask blank consisting of an opaque layer of MoSi on a glass substrate, referred to simply as OMOG. First, OMOG lithographic performance will be compared to a previous chrome/MoSi/glass binary intensity mask (BIM) blank. Standard 70-nm chrome on class (COG) was not considered, as it failed to meet mask-making requirements. Theory and a series of simulation and experimental studies show OMOG to outperform BIM, particularly due to electromagnetic effects and optical proximity correction (OPC) predictability concerns, as OMOG behaves very similarly to the ideal thin mask approximation (TMA). A new TMA-predictability metric is defined as a means to compare mask blanks. We weigh the relative advantages and disadvantages of OMOG compared to 6% attenuated phase shifting. Although both mask blanks are likely sufficient for the 32-nm and 22-nm nodes, some differences exist and are described. Overall, however, of the blanks considered, it is concluded that OMOG provides the most robust and extendable imaging solution available for 32-nm and beyond.
Historically, lithographic scaling was driven by both improvements in wavelength and numerical aperture. Recently,
the semiconductor industry completed the transition to 1.35NA immersion lithography. The industry
is now focusing on double patterning techniques (DPT) as a means to circumvent the limitations of Rayleigh
diffraction. Here, the IBM Alliance demonstrates the extendibility of several double patterning solutions that
enable scaling of logic constructs by decoupling the pattern spatially through mask design or temporally through
innovative processes. This paper details a set of solutions that have enabled early 22 nm learning through careful
The semiconductor industry faces a lithographic scaling limit as the industry completes the transition to 1.35 NA
immersion lithography. Both high-index immersion lithography and EUV lithography are facing technical
challenges and commercial timing issues. Consequently, the industry has focused on enabling double patterning
technology (DPT) as a means to circumvent the limitations of Rayleigh scaling. Here, the IBM development
alliance demonstrate a series of double patterning solutions that enable scaling of logic constructs by decoupling
the pattern spatially through mask design or temporally through innovative processes. These techniques have been
successfully employed for early 32nm node development using 45nm generation tooling. Four different double
patterning techniques were implemented. The first process illustrates local RET optimization through the use of a
split reticle design. In this approach, a layout is decomposed into a series of regions with similar imaging
properties and the illumination conditions for each are independently optimized. These regions are then printed
separately into the same resist film in a multiple exposure process. The result is a singly developed pattern that
could not be printed with a single illumination-mask combination. The second approach addresses 2D imaging
with particular focus on both line-end dimension and linewidth control . A double exposure-double etch (DE2)
approach is used in conjunction with a pitch-filling sacrificial feature strategy. The third double exposure process,
optimized for via patterns also utilizes DE2. In this method, a design is split between two separate masks such that
the minimum pitch between any two vias is larger than the minimum metal pitch. This allows for final structures
with vias at pitches beyond the capability of a single exposure. In the fourth method,, dark field double dipole
lithography (DDL) has been successfully applied to BEOL metal structures and has been shown to be overlay
tolerant . Collectively, the double patterning solutions developed for early learning activities at 32nm can be
extended to 22nm applications.
Optical Proximity Correction (OPC) Model Calibration has required an increasing number of measurements as the
critical dimension tolerances have gotten smaller. Measurement of two dimensional features have been increasing at a
faster rate than features with one dimensional character as the technologies require better accuracy in the OPC models
for line-end pull-back and corner rounding. New techniques are becoming available from metrology tool manufacturers
to produce GDSII contours of shapes from wafers and modeling software has been improved to use these contours.
The challenges of implementing contour generation from the SEM tools will be discussed including calibration methods,
physical dimensions, algorithm derivations, and contour registration, resolution, scan direction, and parameter space
In recent years, design for manufacturability (DFM) has become an important focus item of the semiconductor industry and many new DFM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity, and here we explore the role of through-process modeling on DFM applications. Several different DFM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored, and methods to ensure their accuracy presented.
In this paper, we seek a systematic strategy for creation of a wafer sampling plan and to determine the relationship
between this plan and the OPC model accuracy. We start our study with the traditional error components analysis of
wafer data. From this, we introduce our methodology of calculating the effective sample size based on each pattern and
its error components. With all the error components separated, the confidence of the estimated mean can be calculated
and, hence, an error bar can be added to each mean of the wafer data. This error bar is then used to determine which
patterns are over-fitting and which patterns require an improved fit. We will present a method of providing an optimized
and economical solution for wafer sampling. With this calculated error bar, the ultimate metric for OPC model accuracy
will also be discussed.
We present a comprehensive modeling study of polarization effects for the whole optical chain including exposure tool and mask, with strong emphasis on the impact of the Jones Matrix of the projection lens. First we start with the basic of polarization and then the polarization effect of each components of the optical chain will be discussed. Components investigated are source polarization, rigorous EMF effect, mask blank birefringence, pellicle effect and projection lens. We also focus on comparing the relative merits of different types of representation of Jones matrix of the projection lens and outlined ways to decompose the Jones Matrix. Methodologies such as Pauli matrix, PQM, Jones-Zernike expansion and IPS-Zernike expansion are among the ones investigated. The polarization impact on lithography and OPC on realistic 45nm and 32nm node process levels is discussed. Issues in OPC modeling with Jones Matrix is highlighted. Concerns regarding the standardization of the implementation of Jones Matrix in the lithography community are considered and a standard has been proposed and received wide acceptance. Last we discuss the challenge of using polarization and some novel ideas to deal with polarization in hyper NA era. Throughout the paper the resist component is not included so as to isolate the effect of resist from that of the other components.
Lithography simulation remains one of the primary aspects of most DfM flows, along with critical area analysis and
chem-mech-polish (CMP) modeling. Often, the accuracy of the DfM flow is judged solely on the accuracy of the
lithographic simulation. In this paper we attempt to refute that viewpoint and highlight the many sources of error in a
DfM flow. We examine the factors that impact accuracy and attempt to quantify their effect. Differences between
rigorous simulation, which includes full mask data preparation along with lithography simulation, and the use of
compact models are explored. Required and achievable DfM accuracy over time and across multiple fabs is examined
and the use of a "closed-loop" DfM flow is proposed.
Optimal Proximity Correction (OPC) models are calibrated with Scanning Electron Microscope (SEM) data where the measurement uncertainty vary among pattern types (i.e., line versus space, 1D versus 2D and small versus large). The quality of the SEM measurement uncertainty's impact on OPC model integrity is mitigated through a weighting scheme. Statistical methods such as relating the weight to the SEM measurements standard deviation require more measurements per calibration structure than economically feasible. Similarly, the use of experience and engineering judgment requires many iterations before some reasonable weighting scale is determined. In this paper we present the results of OPC model fitness statistics associated with metrology based weights (MtBW) versus model based weights (MBW). The motivation for the latter approach is the promise for an unbiased, consistent, and efficient estimate of the model parameters.
The impact of mask CD non-uniformity on the accuracy of optical proximity correction (OPC) models has been
observed on several critical levels. In the current OPC model calibration flow, the mask effect is not explicitly separated
from the optical and resist models. Instead, the resist model is compensating for the mask errors. In this paper, we report
a detailed study of the effect of mask CD non-uniformity on OPC model accuracy using the established OPC model
calibration flow. The influence of mask CD non-uniformity on the through process behavior of an OPC model is also
discussed. A possible OPC flow to take the systematic mask CD error into consideration is proposed and a detailed
study of mask modeling is present.
In recent years, design for manufacturability (DfM) has become an important focus item of the semiconductor industry and many new DfM applications have arisen. Most of these applications rely heavily on the ability to model process sensitivity and here we explore the role of through-process modeling on DfM applications. Several different DfM applications are examined and their lithography model requirements analyzed. The complexities of creating through-process models are then explored and methods to ensure their accuracy presented.
The need for accurate quantification of all aspects of design for manufacturability using a mutually compatible set of quality-metrics and units-of-measure, is reiterated and experimentally verified. A methodology to quantify the lithography component of manufacturability is proposed and its feasibility demonstrated. Three stages of lithography manufacturability assessment are described: process window analysis on realistic integrated circuits following layout manipulations for resolution enhancement and the application of optical proximity correction, failure sensitivity analysis on simulated achievable dimensional bounds (a.k.a. variability bands), and yield risk analysis on iso-probability bands. The importance and feasibility of this technique is demonstrated by quantifying the lithography manufacturability impact of redundant contact insertion and Critical Area optimization in units that can be used to drive an overall layout optimization. The need for extensive experimental calibration and improved simulation accuracy is also highlighted.
We report some new results in the use of high energy radiation in proximity x-ray lithography for the 50 nm node. The higher energy of the incoming radiation, 2.6-2.7 KeV, has two primary benefits: (1) it reduces the diffraction and allows printing of higher resolution features, and (2) it increases the effective depth of exposure allowing larger gap setting; however, the absorption of these photons creates hot electrons, which redistributes the energy in the resist, thus creating a uniform blur that limits the resolution by reducing contrast. The impact of the energy redistribution needs to be investigated when increasing the energy of the radiation, and in considering the materials used in both the optics and the mask and resist combination.