Mr. George E. Bailey Profile

George E. Bailey

Director, Technical Marketing at Synopsys Inc

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Publications (21)

Proceedings Article | 4 March 2010 Paper

Impact of scanner signatures on optical proximity correction

Jacek Tyminski, Tomoyuki Matsuyama, Yen-Liang Lu, Jun-Cheng Lai, Kao-Tun Chen, Yung-Ching Mai, Irene Su, George Bailey

Proc. SPIE. 7640, Optical Microlithography XXIII

KEYWORDS: Optical proximity correction, Scanners, Photomasks, Fiber optic illuminators, Cadmium, Integrated circuits, Metrology, Tolerancing, Integrated optics, Diffraction

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Proceedings Article | 31 October 2007 Paper

Safe interpolation distance for VT5 resist model

Walid Tawfic, Mohamed Al-Imam, George Bailey

Proc. SPIE. 6730, Photomask Technology 2007

KEYWORDS: Process modeling, Data modeling, Calibration, Image processing, Optical proximity correction, Lithography, Semiconducting wafers, Geometrical optics, Printing, Integrated circuits

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Proceedings Article | 12 April 2007 Paper

SEM-contour-based OPC model calibration through the process window

Jim Vasek, Ovadya Menedeva, Dan Levitzky, Ofer Lindman, Youval Nemadi, George Bailey, John Sturtevant

Proc. SPIE. 6518, Metrology, Inspection, and Process Control for Microlithography XXI

KEYWORDS: Calibration, Optical proximity correction, Scanning electron microscopy, Process modeling, Data modeling, Databases, Metrology, Semiconducting wafers, Detection and tracking algorithms, Visualization

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Proceedings Article | 28 March 2007 Paper

Circuit-based SEM contour OPC model calibration

Kyle Patterson, Jim Vasek, Chi Min Yuan, George Bailey, Ir Kusnadi, Thuy Do, John Sturtevant

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Calibration, Optical proximity correction, Data modeling, Scanning electron microscopy, Model-based design, Critical dimension metrology, Process modeling, Manufacturing, Data processing, Metrology

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Proceedings Article | 28 March 2007 Paper

Feedback flow to improve model-based OPC calibration test patterns

Walid Tawfic, Mohamed Al-Imam, Karim Madkour, Rami Fathy, Ir Kusnadi, George Bailey

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Calibration, Data modeling, Image processing, Process modeling, Scanning electron microscopy, Optical proximity correction, Photoresist processing, Feature extraction, Optical lithography, Printing

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Proceedings Article | 27 March 2007 Paper

SEM image contouring for OPC model calibration and verification

Cyrus Tabery, Hidetoshi Morokuma, Ryoichi Matsuoka, Lorena Page, George Bailey, Ir Kusnadi, Thuy Do

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Calibration, Scanning electron microscopy, Optical proximity correction, Data modeling, Image processing, Edge detection, Process modeling, Metrology, Critical dimension metrology, Image quality

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Lithography models for leading-edge OPC and design verification must be calibrated with empirical data, and this data is traditionally collected as a one-dimensional quantification of the features acquired by a CD-SEM. Two-dimensional proximity features such as line-end, bar-to-bar, or bar-to-line are only partially characterized because of the difficulty in transferring the complete information of a SEM image into the OPC model building process. A new method of two-dimensional measurement uses the contouring of large numbers of SEM images acquired within the context of a design based metrology system to drive improvement in the quality of the final calibrated model. Hitachi High-Technologies has continued to develop "full automated EPE measurement and contouring function" based on design layout and detected edges of SEM image. This function can measure edge placement error everywhere in a SEM image and pass the result as a design layout (GDSII) into Mentor Graphics model calibration flow. Classification of the critical design elements using tagging scripts is used to weight the critical contours in the evaluation of model fitness. During process of placement of the detected SEM edges of into the coordinate system of the design, coordinate errors inevitably are introduced because of pattern matching errors. Also, line edge roughness in 2D features introduces noise that is large compared to the model building accuracy requirements of advanced technology nodes. This required the development of contour averaging algorithms. Contours from multiple SEM images are acquired of a feature and averaged before passing into the model calibration. This function has been incorporated into the prototype Calibre Workbench model calibration flow. Based on these methods, experimental data is presented detailing the model accuracy of a 45nm immersion lithography process using traditional 1D calibration only, and a hybrid model calibration using SEM image contours and 1D measurement results. Error sources in the contouring are assessed and reported on including systematic and random variation in the contouring results.

Proceedings Article | 26 March 2007 Paper

SEM based data extraction for model calibration

Mohamed Al-Imam, H. Y. Liao, Jochen Schacht, George Bailey, Te Hung Wu, Chia Wei Huang, Sheng Yuan Huang, Pei Ru Tsai, Chuen Huei Yang

Proc. SPIE. 6520, Optical Microlithography XX

KEYWORDS: Data modeling, Scanning electron microscopy, Calibration, Process modeling, Image processing, Optical proximity correction, Semiconducting wafers, Metrology, Resolution enhancement technologies, Feature extraction

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The model calibration process, in a resolution enhancement technique (RET) flow, is one of the most critical steps towards building an accurate OPC recipe. RET simulation platforms use models for predicting latent images in the wafer due to exposure of different design layouts. Accurate models can precisely capture the proximity effects for the lithographic process and help RET engineers build the proper recipes to obtain high yield. To calibrate OPC models, test geometries are created and exposed through the lithography environment that we want to model, and metrology data are collected for these geometries. This data is then used to tune or calibrate the model parameters. Metrology tools usually provide critical dimension (CD) data and not edge placement error (EPE - the displacement between the polygon and resist edge) data however model calibration requires EPE data for simulation. To work around this problem, only symmetrical geometries are used since, having this constraint, EPE can be easily extracted from CD measurements. In real designs, it is more likely to encounter asymmetrical structures as well as complex 2D structures that cannot easily be made symmetrical, especially when we talk about technology nodes for 65nm and beyond. The absence of 2D and asymmetric test structures in the calibration process would require models to interpolate or extrapolate the EPE's for these structures in a real design. In this paper we present an approach to extract the EPE information from both SEM images and contours extracted by the metrology tools for structures on test wafers, and directly use them in the calibration of a 55nm poly process. These new EPE structures would now mimic the complexity of real 2D designs. Each of these structures can be individually weighed according to the data variance. Model accuracy is then compared to the conventional method of calibration using symmetrical data only. The paper also illustrates the ability of the new flow to extract more accurate measurement out of wafer data that are more immune to errors compared to the conventional method.

Proceedings Article | 21 March 2007 Paper

Double pattern EDA solutions for 32nm HP and beyond

George Bailey, Alexander Tritchkov, Jea-Woo Park, Le Hong, Vincent Wiaux, Eric Hendrickx, Staf Verhaegen, Peng Xie, Janko Versluijs

Proc. SPIE. 6521, Design for Manufacturability through Design-Process Integration

KEYWORDS: Double patterning technology, Photomasks, Optical proximity correction, Optical lithography, Metals, Electronic design automation, Etching, Manufacturing, Logic, Image processing

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The fate of optical-based lithography hinges on the ability to deploy viable resolution enhancement techniques (RET). One such solution is double patterning (DP). Like the double-exposure technique, double patterning is a decomposition of the design to relax the pitch that requires dual masks, but unlike double-exposure techniques, double patterning requires an additional develop and etch step, which eliminates the resolution degradation due to the cross-coupling that occurs in the latent images of multiple exposures. This additional etch step is worth the effort for those looking for an optical extension [1]. The theoretical k₁ for a double-patterning technique of a 32nm half-pitch (HP) design for a 1.35NA 193nm imaging system is 0.44 whereas the k₁ for a single-exposure technique of this same design would be 0.22 [2], which is sub-resolution. There are other benefits to the DP technique such as the ability to add sub-resolution assist features (SRAF) in the relaxed pitch areas, the reduction of forbidden pitches, and the ability to apply mask biases and OPC without encountering mask constraints. Similarly to AltPSM and SRAF techniques one of the major barriers to widespread deployment of double patterning to random logic circuits is design compliance with split layout synthesis requirements [3]. Successful implementation of DP requires the evolution and adoption of design restrictions by specifically tailored design rules. The deployment of double patterning does spawn a couple of issues that would need addressing before proceeding into a production environment. As with any dual-mask RET application, there are the classical overlay requirements between the two exposure steps and there are the complexities of decomposing the designs to minimize the stitching but to maximize the depth of focus (DoF). In addition, the location of the design stitching would require careful consideration. For example, a stitch in a field region or wider lines is preferred over a transistor region or narrower lines. The EDA industry will be consulted for these sound automated solutions to resolve double-patterning sensitivities and to go beyond this with the coupling of their model-based and process-window applications. This work documented the resolution limitations of single exposure, and double-patterning with the latest hyper-NA immersion tools and with fully optimized source conditions. It demonstrated the best known methods to improve design decomposition in an effort to minimize the impact of mask-to-mask registration and process variance. These EDA solutions were further analyzed and quantified utilizing a verification flow.

Proceedings Article | 20 March 2006 Paper

Intensive 2D SEM model calibration for 45nm and beyond

George Bailey, Thuy Do, Yuri Granik, Ir Kusnadi, Andrew Estroff

Proc. SPIE. 6154, Optical Microlithography XIX

KEYWORDS: Scanning electron microscopy, Calibration, Data modeling, Process modeling, Image processing, Critical dimension metrology, Optical calibration, Metrology, Electron microscopes, Optical proximity correction

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Proceedings Article | 15 March 2006 Paper

EMF simulation with DDM to enable EAPSM masks in 45-nm manufacturing

Patrick Martin, C. Progler, Michael Cangemi, Kostas Adam, George Bailey, Pat LaCour

Proc. SPIE. 6154, Optical Microlithography XIX

KEYWORDS: SRAF, Polarization, Photomasks, Data modeling, Optical proximity correction, Refractive index, Manufacturing, System on a chip, Critical dimension metrology, Resolution enhancement technologies

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Proceedings Article | 9 November 2005 Paper

Integrated post tape outflow for fast design to mask turn-around time

Chi-Yuan Hung, Qingwei Liu, Liguo Zhang, Shumay Shang, George Bailey, Andrew Jost, Travis Brist

Proc. SPIE. 5992, 25th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Optical proximity correction, Photomasks, Data modeling, Back end of line, Semiconducting wafers, Visualization, Databases, Scanning electron microscopy, Data integration, Metals

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Proceedings Article | 8 November 2005 Paper

Reverse engineering source polarization error

George Bailey, Kostas Adam, Travis Brist, Olivier Toublan, Andrew Estroff

Proc. SPIE. 5992, 25th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Polarization, Data modeling, Reverse modeling, Error analysis, Immersion lithography, Reverse engineering, Critical dimension metrology, Semiconducting wafers, Calibration, Lithography

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Proceedings Article | 8 November 2005 Paper

Source polarization and OPC effects on illumination optimization

Travis Brist, George Bailey, Alexander Drozdov, Andres Torres, Andrew Estroff, Eric Hendrickx

Proc. SPIE. 5992, 25th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Optical proximity correction, Polarization, Lithographic illumination, Lithography, Visualization, Immersion lithography, Fiber optic illuminators, Optical design, Scanners, Data modeling

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Proceedings Article | 12 May 2005 Paper

Polarization influences through the optical path

George Bailey, Kostas Adam

Proc. SPIE. 5754, Optical Microlithography XVIII

KEYWORDS: Polarization, Photomasks, Resolution enhancement technologies, 3D modeling, Lithography, Diffraction, Nanoimprint lithography, Optical proximity correction, Binary data, Systems modeling

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Proceedings Article | 6 December 2004 Paper

Distributed processing in integrated data preparation flow

Steffen Schulze, George Bailey

Proc. SPIE. 5567, 24th Annual BACUS Symposium on Photomask Technology

KEYWORDS: Optical proximity correction, Databases, Parallel processing, Distributed computing, Data processing, Photomasks, Data storage, Data integration, Computing systems, Manufacturing

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Proceedings Article | 10 July 2003 Paper

Effective multicutline QUASAR illumination optimization for SRAM and logic

Travis Brist, George Bailey

Proc. SPIE. 5042, Design and Process Integration for Microelectronic Manufacturing

KEYWORDS: Optical proximity correction, Lithographic illumination, Logic, Manufacturing, SRAF, Lithography, Reticles, Optimization (mathematics), Cadmium, Semiconducting wafers

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Lithographers face many hurdles to achieve the ever-shrinking process design rules (PDRs). Proximity effects are becoming more and more an issue requiring model-based Optical Proximity Correction (OPC), sub-resolution assist features, and properly tuned illumination settings in order to minimize these effects while providing enough contrast to maintain a viable process window. For any type of OPC application to be successful, a fundamental illumination optimization must first be completed. Unfortunately, the once trivial illumination optimization has evolved into a major task for ASIC houses that require a manufacturable process window for isolated logic structures as well as dense SRAM features. Since these features commonly appear on the same reticle, today’s illumination optimization must look at “common” process windows for multiple cutlines that include a variety of different feature types and pitches. This is a daunting task for the current single feature simulators and requires a considerable amount of simulation time, engineering time, and fab confirmation data in order to come up with an optimum illumination setting for such a wide variety of features. An internal Illumination Optimization (ILO) application has greatly simplified this process by allowing the user to optimize an illumination setting by simultaneously maximizing the “combined” DOF (depth of focus) over multiple cutlines (simulation sites). Cutlines can be placed on a variety of structures in an actual design as well as several key pitches. Any number of the cutlines can be constrained to the gds drawn CD (critical dimension) while others can be allowed to “float” with pseudo OPC allowing the co-optimization of the illumination setting for any OPC that may be applied in the final design. The automated illumination optimization is then run using a tuned model. Output data is a suggested illumination setting with supporting data used to formulate the recommendation. This paper will present the multi-cutline ILO process and compare it with the work involved to do the same optimization using a single feature simulator. Examples will be shown where multi-cutline ILO was able to resolve hard annular aberrations while maintaining the DOF.

Proceedings Article | 26 June 2003 Paper

Dark-field high-transmission chromeless lithography

George Bailey, Neal Callan, Kunal Taravade, John Jensen, Benjamin Eynon, Patrick Martin, Henry Kamberian, Darren Taylor, Rick Farnbach

Proc. SPIE. 5040, Optical Microlithography XVI

KEYWORDS: Photomasks, Opacity, Scattering, Lithography, Diffraction gratings, Scanning electron microscopy, Manufacturing, Attenuators, Finite element methods, Optical design

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Proceedings Article | 30 July 2002 Paper

Reticle process effects on OPC models

Travis Brist, George Bailey

Proc. SPIE. 4691, Optical Microlithography XV

KEYWORDS: Photomasks, Optical proximity correction, Reticles, Data modeling, Process modeling, Semiconducting wafers, Scanning electron microscopy, Image processing, Etching, Deep ultraviolet

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Proceedings Article | 30 July 2002 Paper

OPC applications into embedded-OPC designs

George Bailey, Travis Brist

Proc. SPIE. 4691, Optical Microlithography XV

KEYWORDS: Optical proximity correction, Model-based design, Transistors, Process modeling, Photomasks, Logic, Etching, Optimization (mathematics), Photoresist processing, Data modeling

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Proceedings Article | 23 June 2000 Paper

Progressions in deep-ultraviolet bottom antireflective coatings

George Bailey, Nicholas Eib, Earnest Murphy

Proc. SPIE. 3999, Advances in Resist Technology and Processing XVII

KEYWORDS: Semiconducting wafers, Etching, Silicon, Deep ultraviolet, Reflectivity, Thin film coatings, Photoresist processing, Bottom antireflective coatings, Cadmium, Inspection

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Proceedings Article | 2 June 2000 Paper

Utilizing in-line CD SEMs for intensive field mapping

Margaret Fyfield, George Bailey, Waiman Ng, Mohsen Ahmadian

Proc. SPIE. 3998, Metrology, Inspection, and Process Control for Microlithography XIV

KEYWORDS: Critical dimension metrology, Reticles, Semiconducting wafers, Scanning electron microscopy, Scanners, Error analysis, Metrology, Etching, Manufacturing, Associative arrays

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Showing 5 of 21 publications

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