As the industry pushes to ever more complex illumination schemes to increase resolution for next generation memory and logic circuits, sub-resolution assist feature (SRAF) placement requirements become increasingly severe. Therefore device manufacturers are evaluating improvements in SRAF placement algorithms which do not sacrifice main feature (MF) patterning capability. There are known-well several methods to generate SRAF such as Rule based Assist Features (RBAF), Model Based Assist Features (MBAF) and Hybrid Assisted Features combining features of the different algorithms using both RBAF and MBAF. Rule Based Assist Features (RBAF) continue to be deployed, even with the availability of Model Based Assist Features (MBAF) and Inverse Lithography Technology (ILT). Certainly for the 3x nm node, and even at the 2x nm nodes and lower, RBAF is used because it demands less run time and provides better consistency. Since RBAF is needed now and in the future, what is also needed is a faster method to create the AF rule tables. The current method typically involves making masks and printing wafers that contain several experiments, varying the main feature configurations, AF configurations, dose conditions, and defocus conditions – this is a time consuming and expensive process. In addition, as the technology node shrinks, wafer process changes and source shape redesigns occur more frequently, escalating the cost of rule table creation. Furthermore, as the demand on process margin escalates, there is a greater need for multiple rule tables: each tailored to a specific set of main-feature configurations. Model Assisted Rule Tables(MART) creates a set of test patterns, and evaluates the simulated CD at nominal conditions, defocused conditions and off-dose conditions. It also uses lithographic simulation to evaluate the likelihood of AF printing. It then analyzes the simulation data to automatically create AF rule tables. It means that analysis results display the cost of different AF configurations as the space grows between a pair of main features. In summary, model based rule tables method is able to make it much easier to create rule tables, leading to faster rule-table creation and a lower barrier to the creation of more rule tables.
Lithographers had hoped that single patterning would be enabled at the 20nm node by way of EUV lithography. However, due to delays in EUV readiness, double patterning with 193i lithography is currently relied upon for volume production for the 20nm node’s metal 1 layer. At the 14nm and likely at the 10nm node, LE-LE-LE triple patterning technology (TPT) is one of the favored options [1,2] for patterning local interconnect and Metal 1 layers. While previous research has focused on TPT for contact mask, metal layers offer new challenges and opportunities, in particular the ability to decompose design polygons across more than one mask. The extra flexibility offered by the third mask and ability to leverage polygon stitching both serve to improve compliance. However, ensuring TPT compliance – the task of finding a 3-color mask decomposition for a design – is still a difficult task. Moreover, scalability concerns multiply the difficulty of triple patterning decomposition which is an NP-complete problem. Indeed previous work shows that network sizes above a few thousand nodes or polygons start to take significantly longer times to compute [3], making full chip decomposition for arbitrary layouts impractical. In practice Metal 1 layouts can be considered as two separate problem domains, namely: decomposition of standard cells and decomposition of IP blocks. Standard cells typically include only a few 10’s of polygons and should be amenable to fast decomposition. Successive design iterations should resolve compliance issues and improve packing density. Density improvements are multiplied repeatedly as standard cells are placed multiple times. IP blocks, on the other hand, may involve very large networks. This paper evaluates multiple approaches to triple patterning decomposition for the Metal 1 layer. The benefits of polygon stitching, in particular, the ability to resolve commonly encountered non-compliant layout configurations and improve packing density, are weighed against the increased difficulty in finding an optimized, legal decomposition and coping with the increased scalability challenges.
For patterning the upper Metal layers of the 10 nm node, Spacer Is Dielectric (SID) Patterning is the leading candidate. Compared to Litho-Etch-Litho-Etch Double Patterning, SID has lower line-width roughness, tighter line-end spacing, and lower sensitivity to overlay errors. However, SID places more restrictions on design, and creates wafer-printing artifacts or “spurs.” These printing artifacts arise because SID uses a subtractive trim etch to create “negative contours,” which are very different from the positive contours of single-exposure patterning. In this work, we show the origin of these spurs, and present rule-based decomposition methods to avoid or mitigate them.
Self-Aligned Double Patterning (SADP) is a strong candidate for the lower-Metal layers of the 14 nm node. Compared
to Litho-Etch-Litho-Etch (LELE) Double Patterning, SADP has lower LWR (line-width roughness), tighter line-end
minimum spacing, and lower sensitivity to overlay errors. However, design for SADP is more restricted than for LELE.
This work explores the design of layouts compatible with the Spacer Is Dielectric (SID) flavor of SADP. It is easy to
find layouts that are LELE-compliant but not SID-compliant. One reason is that polygon stitching is not allowed in SID.
Another is that certain drawn-space values are forbidden in SID. In this paper, we will write down some basic rules for
SID-compliant design, and introduce some SID-printing artifacts that may be worrisome.
The upcoming 14nm logic node will require lithographic patterning of complex layout patterns with minimum pitches of approximately 44nm to 50nm. This requirement is technically feasible by reusing existing 20nm litho-etch-litho-etch (LELE) double patterning (DPT) methods with very strong restricted design rules. However, early indications are that the cost-effective design and patterning of these layouts will require lithographic methods with additional resolution, especially in two-dimensional configurations. If EUV lithography reaches maturity too late, the 14nm logic node will need other lithographic techniques and the corresponding physical design rules and EDA methodologies to be available. Triple patterning technology (TPT) is a strong option for 14nm node logic on both hole and line-space pattern layers. In this paper we study major implications of a 14nm logic TPT lithographic solution upon physical design, design rules, mask synthesis/EDA algorithms and their process interactions.
Model-based assist-feature (MBAF) placement has been shown to have considerable lithographic benefits vs. rule-based
assist-feature (RBAF) placement for advanced technology-node requirements. For very strong off-axis illumination,
MBAF-placement methods offer improved process window, especially for so-called forbidden pitch regions, and greatly
simplified tuning of AF-placement parameters. Historically, however, MBAF-placement methods had difficulties with
full-chip runtime, friendliness to mask manufacturing (e.g., mask rule checks or MRCs), and methods to ensure that
placed AFs do not print on-wafer. Therefore, despite their known limitations, RBAF-placement methods were still the
industry de facto solution through the 45 nm technology node. In this paper, we highlight recent manufacturability
advances for MBAFs by a detailed comparison of MBAF and RBAF methods. The MBAF method employed uses
Inverse Mask Technology (IMT) to optimize AF placement, size, shape, and software runtime, to meet the production
requirements of the 28 nm technology node and below. MBAF vs. RBAF results are presented for process window
performance, and MBAF vs. OPC results are presented for full-chip runtimes. The final results show that MBAF
methods have process-window advantages for technology nodes below 45 nm, with runtimes that are comparable to
OPC.
In this paper we study interactions of double patterning technology (DPT) with lithography, optical proximity correction (OPC) and physical design flows for the 22-nm device node. DPT methods decompose the original design intent into two individual masking layers, which are each patterned using single exposures and existing 193-nm lithography tools. Double exposure and etch patterning steps create complexity for both process and design flows. DPT decomposition is a critical software step that will be performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of original design intent polygons into multiple polygons, where required, and coloring of the resulting polygons. We evaluate the ability to meet key physical design goals, such as reduce circuit area, minimize relayout effort, ensure DPT compliance, guarantee patterning robustness on individual layer targets, ensure symmetric wafer results, and create uniform wafer density for the individual patterning layers.
A variety of innovations including the reduction of actinic wavelength, an increase in lens NA, an
introduction of immersion process, and an aggressive OPC/RET technique have enabled device shrinkage
down to the current 45nm node. The immaturity of EUV and high index immersion, have made logic
manufacturers look at other ways of leveraging existing exposure technologies as they strive to develop
process technology for 32nm and below. For design rules for sub-nodes from 32nm to 22nm, the need to
define critical layers with double photolithography and etch process becomes increasingly evident.
Double patterning can come in a variety of forms or 'flavors'. For 32/28nm node, the patterning of 2D
features is so challenging that opposing line-ends can only be defined using an additional litho and etch
step to cut them. For 22nm node, even line/space gratings are below the theoretical k1=0.25 imaging limit.
Therefore pitch-doubling double patterning decomposition is absolutely required. Each double patterning
technology has its own set of challenges. Most of all, an existing design often cannot be shrunk blindly and
then successfully decomposed, so an additional set of restrictions is required to make layouts double
patterning compliant. To decompose a logic layout into two masks, polygons often need to be cut so that
they can be patterned using both masks. The electric performance of this cut circuitry may be highly
dependent on the quality of layout decomposition, the circuit characteristics and its sensitivity to
misalignment between the two patterning steps. We used representative logic layouts of metal level and
realistic models to demonstrate the issues involved and attempt to define formal rules to help enable lineend
splitting and pitch-doubling double patterning decomposition. This study used a variety of shrink
approaches to existing legacy layouts to evaluate double patterning compliance and a careful set-up of
parameters for the pitch splitting decomposition engine. The quality of the resultant imaging was tuned
using double patterning aware OPC and printability verification tools.
Double patterning technology (DPT) is one of the main options for printing critical layers at
32nm half-pitch and beyond. To enable DPT, a layout decomposition tool is first used to split the
original design into two separate decomposed-design layouts. Each decomposed-design layout
may then receive optical proximity correction (OPC) and RETs to produce a mask layout. The
requirements for OPC to enable individual layer DPT patterning are generally the same as
current single exposure OPC requirements, meaning that the success criteria will be similar to
previous node specifications. However, there are several new challenges for OPC with DPT.
These include large litho-etch biases, two sets of process variables associated with each
patterning layer and the relative pattern placement between them. The order of patterning may be
important as there may be process interactions between the two patterns especially at overlap
regions. Corners which were rounded in single patterning layers may now become sharp,
potentially increasing reliability concerns due to electromigration. In this study, we address many
of these issues by proposing several new techniques that can be used in OPC with DPT. They
are specifically designed for the Litho-Etch-Litho-Etch process, but some of the ideas may be
extended to develop OPC methods for other DPT processes. We applied the new OPC method to
several circuit and test patterns and demonstrated how OPC results were improved compared to
regular OPC methods.
For keeping pace with Moore's Law of reducing the feature sizes on integrated circuits, the driving forces have been
reductions in the exposure-tool wavelength, and increases in the lens numerical aperture (NA). With extreme ultra-violet
(EUV) lithography and 3rd-generation immersion delayed for production use, these driving forces are now stalled at a
wavelength of 193 nm and an NA of 1.35. Therefore, double-patterning technology (DPT) is needed for printing 22 nm
device node features. With DPT, a 22 nm layout is split into two patterns. Each pattern is printed using 32 nm node
lithography technology, and the original pattern is recovered by a logical summation (the Boolean OR operation) of
these two separately exposed patterns. DPT presents several challenges for printability verification. First, the etch target
can be very different from the resist target because significant biasing is used to improve the lithography process
window. Second, overlaps between the two patterns produce new problems such as sharp-cornered pinching at pattern
junctions, and bridging between patterns. Finally, there are additional process variations: misalignment between the two
patterns, and twice as many dose and defocus dimensions. We present results from a full-chip DPT-verification tool that
addresses these challenges. We also provide examples of lithography problems that are specific to DPT, and describe
possible guidance for the resolution enhancement techniques (RET) and design tools.
Double patterning has gained prominence as the most likely lithographic methodology to help keep Moore's law going
towards 32nm 1/2 pitch lithography. While solutions, to date, have focused mainly on gap splitting to avoid minimum
spacing violations, the decomposition should, ideally, also attempt to optimize the process window of the decomposed
masks. A major contributor to process window sensitivity is the correct placement of sub-resolvable assist features.
These features are placed once the polygons of each mask are defined, i.e. post decomposition. If some awareness of this
downstream process step is made available to the double patterning decomposition stage, then a more robust
decomposition can be achieved.
Double patterning technology (DPT) is one of the main options for printing logic devices with half-pitch
less than 45nm; and flash and DRAM memory devices with half-pitch less than 40nm. DPT methods
decompose the original design intent into two individual masking layers which are each patterned using
single exposures and existing 193nm lithography tools. The results of the individual patterning layers
combine to re-create the design intent pattern on the wafer. In this paper we study interactions of DPT with
lithography, masks synthesis and physical design flows. Double exposure and etch patterning steps create
complexity for both process and design flows. DPT decomposition is a critical software step which will be
performed in physical design and also in mask synthesis. Decomposition includes cutting (splitting) of
original design intent polygons into multiple polygons where required; and coloring of the resulting
polygons. We evaluate the ability to meet key physical design goals such as: reduce circuit area; minimize
rework; ensure DPT compliance; guarantee patterning robustness on individual layer targets; ensure
symmetric wafer results; and create uniform wafer density for the individual patterning layers.
Delays in equipment availability for both Extreme UV and High index immersion have led to a growing
interest in double patterning as a suitable solution for the 22nm logic node. Double patterning involves
decomposing a layout into two masking layers that are printed and etched separately so as to provide the
intrinsic manufacturability of a previous lithography node with the pitch reduction of a more aggressive
node. Most 2D designs cannot be blindly shrunk to run automatically on a double patterning process and so
a set of guidelines for how to layout for this type of flow is needed by designers. While certain classes of
layout can be clearly identified and avoided based on short range interactions, compliance issues can also
extend over large areas of the design and are hard to recognize. This means certain design practices should
be implemented to provide suitable breaks or performed with layout tools that are double patterning
compliance aware. The most striking set of compliance errors result in layout on one of the masks that is at
the minimum design space rather than the relaxed space intended. Another equally important class of
compliance errors is that related to marginal printability, be it poor wafer overlap and/or poor process
window (depth of focus, dose latitude, MEEF, overlay). When decomposing a layout the tool is often
presented with multiple options for where to cut the design thereby defining an area of overlap between the
different printed layers. While these overlap areas can have markedly different topologies (for instance the
overlap may occur on a straight edge or at a right angled corner), quantifying the quality of a given overlap
ensures that more robust decomposition solutions can be chosen over less robust solutions. Layouts which
cannot be decomposed or which can only be decomposed with poor manufacturability need to be
highlighted to the designer, ideally with indications on how best to resolve this issue. This paper uses an
internally developed automated double pattern decomposition tool to investigate design compliance and
describes a number of classes of non-conforming layout. Tool results then provide help to the designer to
achieve robust design compliant layout.
As the technology node shrinks, printed-wafer shapes show progressively less similarity to the design-layout shapes, even with optical proximity correction (OPC). Design tools have a restricted ability to address this shape infidelity. Their understanding of lithography effects is limited, taking the form of design rules that try to prevent "Hot Spots" - locations that demonstrate wafer-printing problems. These design rules are becoming increasingly complex and therefore less useful in addressing the lithography challenges. Therefore, design tools that have a better understanding of lithography are becoming a necessity for technology nodes of 65 nm and below. The general goal of this work is to correct lithography Hot Spots during physical-design implementation. The specific goal is to automatically fix a majority of the Hot Spots in the Metal 2 layers and above, with a run time on the order of a few hours per layer. Three steps were taken to achieve this goal. First, Hot Spot detection was made faster by using rule-based detection. Second, Hot Spot correction was automated by using rule-based correction. Third, convergence of corrections was avoided by performing correction locally, which means that correcting one Hot Spot was very unlikely to create new Hot Spots.
Simulation-based scoring of mask defects is useful for technology nodes of 180 nm and below since wafer shapes can be quite different from those on the mask, and therefore not every defect has printing significance. An important issue for simulation-based scoring is calibrating the resist model. Calibration data is scarce for a variety of reasons, among them, (i) the mask shop is not privy to it, and (ii) the reticle-inspection machine may not visit calibration locations. Specifically, while is relatively easy to obtain the target critical dimension (CD) - the intended value of the smallest wafer CD for that mask, the cutline position for that target CD is uncertain. This work focuses on calibrating the simplest of resist models, a threshold, using only knowledge of the target CD. It quantifies the uncertainty in target cutline position with a probabilistic treatment. This shifts the question from, "What is a good threshold?" to, "What is NOT a bad threshold?" The answer is a range of thresholds that does not print sub-resolution features, and that does not grossly distort the ratio of inspection-image CD to wafer CD. Defect dispositioning is then based on the most pessimistic printability score for that threshold range. Given the uncertainty in resist-model calibration, it is appropriate to be conservative and assume the most pessimistic resist threshold.
The dispositioning of mask defects must also heed the increasing gap between the lithography wavelength and wafer-feature widths. For the larger technology nodes, where printed-wafer shapes are similar to those on the mask, mask-level analysis is sufficient. However, for smaller nodes, wafer-level scoring is useful since every defect does not significantly impact the wafer. Wafer-level analysis often relies on measurements of critical dimension (CD). However, as reticle enhancement technology proliferates, there are increasingly more curved edges where CD cannot be used. For example, false alarms can result from measuring CD near line ends because slight variations in measurement position may produce large CD changes. More importantly, a killer defect may be missed if cutlines are forbidden near line ends because the CD measurements are too far from the defect. Wherever CD measurements are not advisable, we advocate the use of Area scoring by computing the difference in printed feature area. We are not abandoning CD scoring but rather combining it with Area scoring, and using the more pessimistic score. For Area scoring, we use (Defect area - Reference area)/(Reference area). In general, the reference area is difficult to define since many shapes are not easily parsed into primitive shapes. Therefore, we use a square of side equal to the target CD. This square defines the window for a sliding-window average of the area difference. The maximum average value is then chosen from the entire image. Unlike Edge Placement Error, Area is sensitive to long, thin difference regions. Unlike Flux or Maximum Intensity Difference, Area is threshold-aware; it measures what prints and shows process-window variation.
As 90 nm LSI devices are about to enter pre-production, the cost and turn-around time of photomasks for such devices will be key factors for success in device production. Such devices will be manufactured with state-of-the-art 193nm photolithography systems. Photomasks for these devices are being produced with the most advanced equipment, material and processing technologies and yet, quality assurance still remains an issue for volume production. These issues include defect classification and disposition due to the insufficient resolution of the defect inspection system at conventional review and classification processes and to aggressive RETs, uncertainty of the impact the defects have on the printed feature as well as inconsistencies of classical defect specifications as applied in the sub-wavelength era are becoming a serious problem. Simulation-based photomask qualification using the Virtual Stepper System is widely accepted today as a reliable mask quality assessment tool of mask defects for both the 180 nm and 130 nm technology nodes. This study examines the extendibility of the Virtual Stepper System to 90nm technology node. The proposed method of simulation-based mask qualification uses aerial image defect simulation in combination with a next generation DUV inspection system with shorter wavelength (266nm) and small pixel size combined with DUV high-resolution microscope for some defect cases. This paper will present experimental results that prove the applicability for enabling 90nm technology nodes. Both contact and line/space patterns with varies programmed defects on ArF Attenuated PSM will be used. This paper will also address how to make the strategy production-worthy.
For alternating aperture phase shift masks (AAPSM), phase-defect detection and disposition is more difficult for 193 nm (ArF) lithography than for 248 nm (KrF) lithography, as pattern geometry is tighter and quartz etching is shallower. For ArF lithography, we designed and fabricated a new test mask to confirm detectability and printability of phase defects, extending our previous work for KrF lithography. This test mask has precise defect sizes and phase-error angles of 25, 50, and 75 degrees. Detectability was demonstrated on KLA-Tencor’s SLF27 and investigated by acquiring defect images on SLF27 and LaserTec’s MD3000 inspection systems. Printability was compared between actual wafer prints, and simulations from Carl Zeiss’ Aerial Image Measurement System (AIMS). Wafer prints were also simulated using Numerical Technologies’ software-based Virtual Stepper System, which takes inspection images as input and models the optical aspects of lithography. Virtual Stepper critical-dimension measurements show good general agreement with those from AIMS images and wafer-print SEM images. Compared to AIMS, which is a hardware-based simulator that uses the actual mask as input, the software-based Virtual Stepper System is easier to adapt to different processes and to integrate into the production flow.
For alternating aperture phase shift masks (AAPSM) and 193 nm (ArF) lithography, we have simulated defect printability using inspection images and software-based modeling. Masks were fabricated by DuPont Photomasks with programmed defects of known size, phase, and location. Three phase layers were used to generate defect angles 60, 120 and 180 degrees. Simulated wafer prints were performed using Numerical Technologies’ Virtual Stepper System, which takes inspection images as input and models the lithographic process. With inspection images from KLA-Tencor’s SLF27 system, our critical-dimension measurements show good agreement with those from wafers printed on an ASML PAS 5500/900 scanner.
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