This paper describes the critical dimension (CD) accuracy of metal-layer patterns for the 15-nm logic node and beyond
replicated with model-based optical proximity correction, flare variation compensation, and shadowing effect correction.
The model fitting took resist shrinkage during CD measurements into account so as to reduce the modeling error. Since
sufficient accuracy was obtained for various patterns under the assumptions of device production, and since conventional
illumination could be used, it was possible to establish a design rule with few restrictions for the 15-nm node. For the 12-nm logic node, an SRAM pattern for a cell size of 0.0288 μm2 was fabricated using dipole illumination.
Advanced pre-production optics were used to assess the impact of flare on CD variation. Since chemical flare occurs in
SSR4, a top coating was used to prevent acid re-adsorption during the post-exposure bake. The flare due to the optics
was reduced to half that of conventional optics, and the CD variation due to flare was found to be predictable from the
point spread function of the projection optics. This means that the established concept of flare correction is usable with
EUV lithography is considered one of the options for high volume manufacturing (HVM) of 16 nm MPU node devices
. The benefits of high k1(~0.5) imaging enable EUVL to simplify the patterning process and ease design rule
restrictions. However, EUVL with its unique imaging process - reflective optics and masks, vacuum operation, and
lack of pellicle, has several challenges to overcome before being qualified for production. Thus, it is important to
demonstrate the capability to integrate EUVL into existing process flows and characterize issues which could hamper
yield. A patterning demonstration of Intel's 32 nm test chips using the ADT at IMEC  is presented, This test chip
was manufactured using processes initially developed with the Intel MET [2-4] as well as masks made by Intel's mask
shop [5,6]. The 32 nm node test chips which had a pitch of 112.5 nm at the trench layer, were patterned on the ADT
which resulted in a large k1 factor of 1 and consequently, the trench process window was iso-focal with MEEF = 1. It
was found that all mask defects detected by a mask pattern inspection tool printed on the wafer and that 90% of these
originated from the substrate. We concluded that improvements are needed in mask defects, photospeed of the resist,
overlay, and tool throughput of the tool to get better results to enable us to ultimately examine yield.
Extreme ultraviolet lithography (EUVL) tool development achieved a big milestone last year as two full-field
Alpha Demo Tools (ADT) were shipped to customers by ASML. In the future horizon, a full field "EUV1" exposure
tool from Nikon will be available by the end of 20071 and the pre-production EUV exposure tools from ASML are
targeted for 20092. It is essential that high quality EUVL masks can be made and delivered to the EUVL tool users to
support the technology development. In the past year, we have demonstrated mask fabrication with low stress absorber
deposition and good etch process control yielding a vertical etch profile and a mask CD control of 5.7 nm for 32 nm (1x)
space and 7.4 nm for 32 nm (1x) lines. Mask pattern resolution of 15 nm (1x) dense lines was achieved. Full field
reflective mask die-to-die inspection at a 125nm pixel size was demonstrated after low defect multilayer blanks became
In this paper, we will present details of the Intel EUVL Mask Pilot Line progress in EUVL mask defect reduction,
pattern CD performance, program defect mask design and inspection, in-house absorber film development and its
performance, and EUVL metrology tool development. We will demonstrate an overall improvement in EUV mask
manufacturing readiness due to our Pilot Line activities.
It becomes increasingly important to have an integrated process for Extreme UltraViolet (EUV) mask fabrication in order to meet all the requirements for the 32 nm technology node and beyond. Intel Corporation established the EUV mask pilot line by introducing EUV-specific tool sets while capitalizing on the existing photomask technology and utilizing the standard photomask equipment and processes in 2004. Since then, significant progress has been made in
many areas including absorber film deposition, mask patterning optimization, mask blank and patterned mask defect inspection, pattern defect repair, and EUV mask reflectivity metrology. In this paper we will present the EUV mask process with the integrated solution and the results of the mask patterning process, Ta-based in-house absorber film deposition, absorber dry etch optimization, EUV mask pattern defect inspection, absorber defect repair, and mask reflectivity performance. The EUV resist wafer print using the test masks that are fabricated in the EUV mask pilot line will be discussed as well.
Mask defect specifications not only are needed to ensure quality masks for acceptable resist patterning on wafers, but also are utilized as a common goal for tool development, noticeably for mask inspection and repair. Defect specifications are generally determined by the allowable critical dimension (CD) changes from 'defect printability' experiments where a programmed defect mask (PDM) with intentionally placed defects is exposed in a stepper and the changes in resist CDs are measured. With the recent availability of extreme ultra-violet micro-exposure tools (EUV MET), a small field stepper with a numerical aperture (NA) of 0.3, 5X reduction and adjustable degrees of coherence, we are able for the first time to perform extensive studies of pattern defect printability for EUV masks with a high NA exposure tool. Such studies have investigated the defect impact to feature CDs for three different types of patterns: poly gate layer, contacts, and dense lines and spaces. This paper presents the experimental results and analysis of printability data collected under two illumination conditions, annular and dipole, on the MET with full focus and dose matrix (FEM). We have investigated as many as 10 types of defects designed on the PDM for each pattern layer. For each type of defect, a total of 15 sizes are coded on the PDM. With the consideration of limited resolution and line edge roughness of current EUV resists commonly used for EUV lithography development, the CDs under study were chosen in the range of about 40nm to 70nm. Extrapolations from these data are made to predict pattern defect specifications for smaller resist line features. Resist resolution is the main reason for the discrepancies between aerial image simulations and data presented in this paper.
We describe the development of a high-speed, 12-channel (8-data, 2-clock and 2-alignment channels), parallel optical link with a unique packaging concept. The package is used to demonstrate the viability of chip-to-chip optical I/O in very large scale integration (VLSI) circuits. However, for implementation of optical systems in high performance computing applications, the cost of components and packaging has to come down significantly from the traditional optical communication distances. In the current work we attempted to realize such a system by using power efficient optical and electronic components together with a potentially low cost packaging solution compatible with the electronics industry. Vertical Cavity Surface Emitting Lasers (VCSEL), positive-intrinsic-negative (PIN) photodetectors, polymer waveguide arrays as well as CMOS transceiver chip were heterogeneously integrated on a standard microprocessor flip-chip pin grid array (FCPGA) substrate. The CMOS transceiver chip from 0.18μm processing technology contains VCSEL drivers, transimpedance and limiting amplifiers and on-chip self-testing circuits. A self-test circuit in such high-speed systems will be highly beneficial to reduce the testing cost in real products. For fully assembled packages we measured a 3 Gb/s optical eye for the transmitter (24Gb/s aggregate data rate) and a transmission over the complete link was achieved at 1 Gb/s (8Gb/s aggregate data rate).