KEYWORDS: Metals, Design and modelling, 3D acquisition, Wafer bonding, Dysprosium, Back end of line, Semiconducting wafers, Electronic design automation, Logic, 3D image capture
Fine-pitch 3D integration is considered a promising way to advance traditional CMOS scaling as 3D interconnects are currently capable to match the connectivity among functional sub-blocks of a system, enabling their displacement on different tiers. A major bottleneck for 3D ICs is represented by the power delivery, due to the challenge of supplying multiple dies. This work aims to provide insights into the system-level impact of PDN in a 3D chip, in terms of frequency and IR drop. A highly-interconnected memory-dominated SoC is physically implemented using the same 2nm technology in 2D and 3D. For both options, the results are compared with an ideal PDN-less implementation, showing that 3D-induced frequency (up to 9.3%) and wirelength (∼ 10%) benefits are retained upon PDN insertion. From the power integrity perspective, a ∼ 60mV dynamic IR drop improvement is observed in 3D, compared to a conventional frontside PDN in 2D, when considering the 90th percentile of a cumulative distribution function. This work validates the expected technology-driven benefits of 3D integration at the system physical design level, in a realistic environment including a 3D PDN.
KEYWORDS: Design and modelling, Metals, Silicon, Electronic design automation, Nanosheets, Back end of line, Simulations, Resistance, Dielectrics, Tungsten
The backside of the silicon substrate is predicted to be heavily exploited by the next generation of integrated circuits to fulfill the increasingly challenging task of delivering current to billions of transistors. The buried power rail presented in this paper represents an enticing way to start transitioning from the frontside to the backside by moving the power rails in the silicon substrate. This is achieved by leveraging the large portions of Shallow Trench Isolation between fin-based devices. A metal layer is added to a conventional BEOL stack to enable this technology in commercial EDA tools for physical implementation and IR drop analysis. A comprehensive PPA evaluation of the buried power rail is performed at the block level, using a 64-bit CPU block and imec A14 nanosheet PDK. Typical physical design parameters are varied in the process to understand the impact of buried power rail in different conditions. The results show performance improvements both in iso-target (from 2% to 3.5%) and maximum frequency (from 9.5% to 12%). Both stem from a 7% shorter wirelength and 16% smaller area. From the IR drop perspective, better results are obtained with the buried rails showing a reduction up to 33% and enabling the use of sparser power delivery structures. This paper shows how moving the power rails to the substrate represents a powerful block-level knob for power delivery network optimization and as a performance booster.
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