To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection
system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced
operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or
fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer
defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer
basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a
very tedious and time-consuming task and may cause extended manufacturing line-down situations.
Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports
to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation
errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be
spent working on other more productive activities.
This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a
format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical
charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or
entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle
defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing
reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.
To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection
system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced
operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or
fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer
defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer
basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a
very tedious and time-consuming task and may cause extended manufacturing line-down situations.
Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports
to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation
errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be
spent working on other more productive activities.
This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a
format compatible with KLA-Tencor's Klarity DefectTM data analysis database. The objective is to use the graphical
charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or
entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle
defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing
reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.
This paper describes a simple technique to improve the process latitude for contact and via printing. The technique
applies a selective upsizing algorithm to the mask data during the mask preparation step. For each contact or via, the
algorithm looks for available spaces by checking relevant layers near it. When spaces are available, selective edges of a
contact or via will be sized to improve the process latitude. This paper describes algorithms used to implement this
technique. Multiple designs of various design styles are used to demonstrate the effectiveness of the algorithms. The
implications on mask preparation, mask making and wafer processing are also discussed.
Double Process Lithography (DPL) has been widely accepted as a viable printing technique for
critical layers at 45nm nodes and below. In addition, DPL technique also allows us to use available process
tool-sets with less capability to develop the next node CMOS devices in early research and development
stages with additional photo-masks. One practical issue of applying DPL technique is the process crosstalk,
which is the impact of the existing etched patterns after the 1st process to the overall lithography
performance during the 2nd printing process. In this paper, we evaluated the DPL process for contact holetype
patterning with a 193nm silicon-containing bi-layer photo-resist. We explained the bi-layer photoresist
process flow and its low process cross-talk characteristics when applied in our DPL process. We also
discussed the challenges of printing small contacts in the DPL process. The preliminary experiment results
indicated that silicon-containing photo-resist process is a good candidate for DPL process in the contact
hole-type of patterns, and it has good characteristics of low process cross-talk. The flexibility of the drydevelop
process in bi-layer resist also offered us another way to form small contacts in the substrate film.
At the end, we provided some suggestions in contact pattern decomposition algorithm and related
exposure-tool alignment strategies for future implementation of DPL technology.
To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection
system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced
operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or
fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer
defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer
basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a
very tedious and time-consuming task and may cause extended manufacturing line-down situations.
Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports
to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation
errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be
spent working on other more productive activities.
This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a
format compatible with KLA-Tencor's Klarity DefecTM data analysis database. The objective is to use the graphical
charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or
entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle
defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing
reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.
6% attenuated embedded PSM (att-EAPSM) has been widely used in semiconductor wafer
manufacturing industry at 130nm, 90nm, 65nm and 45nm nodes. To effectively use the 6% att-EAPSM
photomask technology and reduce its manufacturing costs, it is important for the industry to develop a
comprehensive mask specification that can fully meet the wafer level lithography requirements without
over-constraining the control parameters in 6% att-EAPSM manufacturing process. In this paper, we used
computer simulation software, Prolith by KLA-Tencor to study the impact of local phase-angle and
transmission errors to wafer lithography process. The simulation results indicated that phase-angle and
transmission errors result in a best focus plane shift, and hence reduce the common focus exposure window
across the mask. The data also indicated that as the NA (numerical aperture) of the lithography system
increases, the same amount of phase-angle error results less amount of focus shift. Based on this study and
the practical common focus windows in semiconductor industry, we proposed a new phase-angle and
transmission specification of 6% att-EAPSM for 90nm, 65nm and 45nm node wafer process.
Across-chip and across-wafer patterned linewidth variation (ACLV and AWLV respectively) as well as linewidth roughness (LWR) are key contributors to device performance variation. For polysilicon gate patterning, the linewidth control enabled by various phase-shift mask (PSM) design approaches is one of the key metrics in selecting the most manufacturable process. Embedded attenuated PSM (6% EAPSM), chromeless PSM (CPL) and alternating aperture PSM (AAPSM) designs were selected for comparison. Polysilicon wafers were exposed with 193nm lithography using these reticles, and then ACLV, AWLV and LWR were measured for each PSM process. The results are discussed and compared with other reticle design factors important for effective 65nm node patterning in production.
As the semiconductor-process technology advances towards the 90nm-node, more and more wafer-fabs start to use 193nm EAPSM (Embedded Attenuated Phase-Shift Mask) technology as the main lithography strategy for the most critical-layers. Because the 193nm EAPSM is a relative new technology in the semiconductor industry, it is important for us to understand the key-mask-specifications in a 193nm EAPSM and their impact to the wafer process windows. In this paper, we studied the effects of phase-angle and transmission to the wafer process window of a 193nm-EAPSM in a 300mm wafer-manufacturing environment. We first fabricated a special multi-phase EAPSM by a combination of extra Quartz-etch and Mosi-removal. We then used a high NA 193nm scanner (ASML-ALTA1100) and high contrast resist to perform the wafer-level printing study. To fully understand the impact of phase-angle and transmission to wafer process windows, we also used AIMS (Aerial-Image Measurement System) and Prolith simulation software to study the lithographic performances of various phase-angle and transmission combinations. By combining the wafer-level resist imaging printing results, AIMS studies and Prolith-2 lithography simulations, we proposed the practical phase-angle and transmission specifications for the 90nm-node wafer process.
Rapidly accelerating technology roadmaps have put increased pressure on in-line process control. CDs measured by automated SEMs are a common element of in-line process control. However, CD measurements alone may not be enough in all cases for adequate process control. For instance, degradation of feature integrity that does not lead to out of control CDs in photo can lead to scrap after etch. The cost of scrap and loss of time to results associated with catching photo process drift with after etch inspection has forced the development of new tools to monitor feature integrity in the ADI CD inspection module. Likewise, partially closed vias that are not caught with etch CD inspection can have a negative impact on copper processes. We describe a feature integrity monitoring technique using an automated CD-SEM that occurs simultaneously with the CD measurement to monitor and detect process drift prior to out of control CD events. We further describe the implementation of this technique in a production environment.
In this paper we present the activities at the Center for X-ray Lithography (CXrL) that are dedicated to applying x-ray lithography to 0.25 micrometers processing. We first present the results of optimizing the parameters of the x-ray resist, AZ-PF 514, to achieve 0.25 micron features with variations of less than 10%; second, we discuss the properties of an exposure station (ES3) that feeds the in-house built aligner; third, we present the novel in-house built Two State Aligner (TSA) and its ability to achieve < 32 nm registration error; fourth, we present a developed fabrication process that produces masks with the required membrane stress, optical transparency, and mask flatness; and finally, we present the integration of all the above subprocesses by showing preliminary results from the in-progress 0.25 micrometers NMOS device run. The requirements and results of each sub-process are discussed and judged according to the 0.25 micrometers error budget goals that were initially set for 1997.
Access to the requested content is limited to institutions that have purchased or subscribe to SPIE eBooks.
You are receiving this notice because your organization may not have SPIE eBooks access.*
*Shibboleth/Open Athens users─please
sign in
to access your institution's subscriptions.
To obtain this item, you may purchase the complete book in print or electronic format on
SPIE.org.
INSTITUTIONAL Select your institution to access the SPIE Digital Library.
PERSONAL Sign in with your SPIE account to access your personal subscriptions or to use specific features such as save to my library, sign up for alerts, save searches, etc.