In this paper, we present a study on the overlay (OVL) shift issue in contact (CT) layer aligned to poly-silicon (short as poly) layer (prior layer) in an advanced technology node [1, 2]. We have showed the wafer level OVL AEI-ADI shift (AEI: After Etch Inspection; ADI: After Developing Inspection; AEI-ADI: AEI minus ADI). Within the shot level map, there exists a center-edge difference. The OVL focus subtraction map can well match the OVL AEI-ADI shift map. Investigation into this interesting correlation finally leads to the conclusion of PR tilt. The film stress of the thick hard mask is responsible for the PR tilt. The method of OVL focus subtraction can therefore be a powerful and convenient tool to represent the OVL mark profile. It is also important to take into account the film deposition when investigating OVL AEI-ADI shift.
KEYWORDS: Critical dimension metrology, Scanning electron microscopy, Electron beams, Metals, Optical proximity correction, Inspection, Process control, Electron microscopes, Semiconductors, Control systems
As the technology node of semiconductor industry is being driven into
more advanced 28 nm and beyond, the critical dimension (CD) error
budget at after-development inspection (ADI) stage and its control are
more and more important and difficult (1-4). 1 nm or even 0.5 nm CD
difference is critical for process control. 0.5~1 nm drift of poly linewidth
will result in a detectable off-target drift of device performance. The
0.5~1 nm CD drift of hole or metal linewidth on the backend interconnecting
layers can potentially contribute to the bridging of metal
patterns to vias, and thereby impact yield. In this paper, we studied one
function in the scanning electron microscope (SEM) measurement, i.e.
the adjustment of brightness and contrast (ABC). We revealed how the
step of addressing focus and even the choice of addressing pattern may
bring in a systematic error into the CD measurement. This provides a
unique insight in the CD measurement and the measurement consistency
of through-pitch (TP) patterns and functional patterns.
Critical dimension uniformity (CDU) of hole layer is becoming more
and more crucial and tightened alongside with the technology node being
driven into 28 nm and beyond, since the critical dimension (CD)
variation of 2-dimensional (2D) hole pattern is intrinsically harder to
control than that of 1D pattern (line/space). As the process window
becomes more marginal with the more advanced technology node,
although at the cost of contrast loss, EFESE tilt (focus drilling method) is
one handy trick for its DOF enhancement capability (1-3). We observed
an abnormal up to 6 nm ADI CD trend-down in Y-direction (exposure
scan direction) in the strictly repeated via-hole patterns within an about 8
mm x 6 mm chip in condition 1 wafer with pre-layer patterns (short as
C1 wafer) where EFESE tilt is applied. No CD trend-down or trend up in
X-direction. This C1 hole layer uses EFESE tilt to improve DOF. This
CD trend-down phenomenon is thoroughly investigated and a model of
“effective EFESE tilt” is proposed and verified. Based on the model, we
made a further step into the assessment of another focus drilling method,
i.e. EFESE High Range (HR) and evaluate its performance under the
same complex leveling scheme. Through all this analysis, we give an
insight of the safety zone for applying EFESE tilt for future reference.
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