KEYWORDS: Resistors, Power supplies, Resistance, Computer simulations, Capacitance, Algorithms, Switching, Inductance, System on a chip, Finite-difference time-domain method
The analysis of full-chip IR and di/dt drop as well as package and on-chip resonance is very important for the system-on-chip design. Algorithms to optimize power distribution networks (PDNs) iteratively require fast methods to estimate the power supply noise. Additionally an efficient way to provide the complex input data for such a simulation is required. The simulation method used is based on a macromodel of the off-chip power supply and a 2D signal line model of the on-chip PDN. The on-chip PDN gets discretized in 2D signal line cells. We use admittance functions in each direction instead of resistances and inductances for these cells. Therefore, the frequency dependence due to the multiple return paths in different layers and further high frequency effects can be incorporated. One of the merits of this approach is that these admittance functions, which may vary all over the chip, can be efficiently calculated with a model order reduction algorithm directly from a Partial Element Equivalent Circuit (PEEC) model. The currents of the nonlinear devices are modeled as time varying current sources in parallel to capacitances and conductances. We use a fast transient simulation algorithm closely related to the Finite-Difference Time-Domain schemes to simulate the model. The method is well suited for iterative design improvements and irregular power grids. Combining the macromodel of the off-chip PDN with the reduced order model of the IC we investigate the effect of damping resistors and the possibility to optimize the power integrity by increasing the damping resistors.
The method for the multi-phase computer-generated-holography (CGH) design of reconfigurable chip or board level optical interconnection is discussed in this paper. First, an improved direct search (DS) algorithm for the multi-phase CGH design is presented. Using this method, the high quality multi-phase CGH can be calculated very quickly, and the computation complexity is much lower than the other algorithms such as the most popularly used DS method and SA method. Then, how to use this algorithm for the CGH design of the reconfigurable chip or board level optical interconnection is given.
For high speed data transmission between different integrated circuits on one circuit board several aspects have to be considered: to avoid reflections a termination at the receiver is needed; to reduce power consumption a low signal swing is required; to make the transmission insensitive to interferences differential signals have to be used. All of this is taken into consideration by using the 'IEEE-Standard for Low-Voltage Differential Signals (LVDS)'. In one part of this standard the specifications for the receiver are given. To fulfill these requirements special amplifier circuits are necessary. They must be able to operate with a very small differential signal at the input (400 mV max.) and a strongly varying operating point (between 0 and 2.4 V). With a supply voltage of 2.5 V two complementary input stages are necessary. Their output signals have to be combined and amplified to full signal swing. Different circuits which fulfill these conditions are presented and compared based on transistor level simulation. To improve the timing behaviour and to increase the signal slope and the opening in the eye diagram the transistor dimensions of the circuits have been optimized by using the optimization tool OPSIM. For the two most promising circuits with a data rate of 1.0 respectively 1.4 GBit/s and a power consumption of approximately 1 respectively 4 mW a full custom layout was created by using a modul generator environment and a design assistant. These two circuits have been realized in a 0.25 μm CMOS technology. Measurement results of the two circiuts are presented.
Nowadays, the delay, the output transition time and the short circuit power consumption of CMOS gates depend on the load capacitance and the input transition time. In currently used technology libraries, table models with 25 or more samples are used for calculating by interpolation each of these three variables. Previous work deriving analytical models are based on neglecting the short circuit current or approximating currents as piecewise linear. In the beginning of this paper, different mathematical models describing the transistor current are compared with respect to the accuracy of a numerical calculated output waveform. The results show that Sakurai's alpha-Power Model with linear equation in the linear region and exponent alpha=1 serves as a well-fitting model for the underlying 0.35 μm technology. Based on this transistor model and the assumption of a linear rising input, the differential equation of the output voltage, including both transistor currents and the capacitive load, has to be solved. Splitting the solution into regions, an approximate solution can be derived for the case that the PMOS transistor is working in linear and the NMOS in saturation condition. The rather complex calculation of the point where the PMOS transistor switches from linear to saturation region can be simplified by using curve fitting techniques. The required curve parameters depend on technology constants as in MM9 and the quotient wn/wp. Consequently, one set of parameters allows the analysis of a wide range of inverters as long as wn/wp is kept constant. The accuracy of the results for the delay are typically within 10%, those for output transition time and power consumption within 5% compared to spice simulation.
KEYWORDS: Gallium arsenide, Logic, Digital electronics, Transistors, Field effect transistors, Switching, Microelectronics, Very large scale integration, Integrated circuits, Digital electronic circuits
There are numerous sources of noise present in the VLSI integrated circuits. A function that can measure the ability of a digital logic circuit to operate error-free in a noisy environment is noise margin which can be define in several ways from the transfer characteristic of the logic circuit. It is critical to be able to precisely evaluate a noise margin for Gallium Arsenide circuits, as its value is usually limited to the extent that only NOR gates are allowed in DCFL digital circuits and NAND gates, where stacked pull down transistors would be required, are excluded. In the paper, the best-case and worst-case static noise margin are discussed and it is shown that not only the load but also the noise voltage has to be included when evaluating a transfer function. Fortunately, the best-case noise margin can still be calculated with the nose free transfer function. But the more useful worst-case noise margin is shown to depend on the transfer function including the noise source. Therefore, as was already pointed out by Lohstroh for CMOS circuits, the best way to calculate the noise margin is to start a quasi-static transient simulation with all noise sources being zero and by increasing the amplitudes of the noise sources slowly compared to the switching speed of the logic circuits. The worst-case noise margin is then found as the noise amplitude at which the chain exhibits a malfunction. Since an infinitely long chain is sown to be equivalent to a flip-flop the flip-flop can be used for the simulation instead. The examples of an inverter and an AND gate illustrate the theory presented.
Conference Committee Involvement (5)
VLSI Circuits and Systems
2 May 2007 | Maspalomas, Gran Canaria, Spain
Microelectronics: Design, Technology, and Packaging II
12 December 2005 | Brisbane, Australia
Smart Structures, Devices, and Systems II
13 December 2004 | Sydney, Australia
Microelectronics: Design, Technology, and Packaging
10 December 2003 | Perth, Australia
VLSI Circuits and Systems
19 May 2003 | Maspalomas, Gran Canaria, Canary Islands, Spain
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