In this paper, we demonstrate an attachable energy-harvester-powered wireless vibration-sensing module for milling-process monitoring. The system consists of an electromagnetic energy harvester, MEMS accelerometer, and wireless module. The harvester consisting of an inductance and magnets utilizes the electromagnetic-induction approach to harvest the mechanical energy from the milling process and subsequently convert the mechanical energy to an electrical energy. Furthermore, through an energy-storage/rectification circuit, the harvested energy is capable of steadily powering both the accelerometer and wireless module. Through integrating the harvester, accelerometer, and wireless module, a self-powered wireless vibration-sensing system is achieved. The test result of the system monitoring the milling process shows the system successfully senses the vibration produced from the milling and subsequently transmits the vibration signals to the terminal computer. Through analyzing the vibration data received by the terminal computer, we establish a criterion for reconstructing the status, condition, and operating-sequence of the milling process. The reconstructed status precisely matches the real status of the milling process. That is, the system is capable of demonstrating a real-time monitoring of the milling process.
Mostly, crown-shaped DRAM capacitor is formed by depositing a series of polysilicon and silicon oxide in a recess followed by etching back to form the vertical side-wall. In this paper, we are proposing a new method which is directly using crown-shaped photoresist pattern in conjunction with the chromless mask (or high transmission half-tone mask) to define the crown structure. A chromless 180 degrees phase shifters on transparent substrate (or high transmission half-tone phase shift mask) is used to create the 'destructive interference' between phase shifters and clear areas at the edges of the phase shifters to define 'dark areas' on the aerial image. The stacked capacitor pattern is defined as phase shifter region, therefore, the 'dark areas' on the edge of the phase shifter becomes the photoresist side-wall after exposing and developing. This crown-shaped resist side-wall then becomes the etching mask to form the crown-shaped capacitors. A special pattern layout of phase shift mask with two groups of phase shifters has been designed to form a double crown-shaped photoresist side- wall. The pattern includes the capacitor node phase shifter and a buffer shifter between two nodes. Lithography simulators, Depict-III, was used to simulate the aerial image intensity distribution of the phase shift mask layout. A single and double crown-shaped aerial image patterns have been simulated. The simulations have shown the results in agreement with the experiments, where a 0.15-0.25 micrometers wide vertical side-wall of a single crown pattern has been obtained. These new capacitors are estimated to increase the capacitance over the conventional thick capacitor by about 50 percent (for single crown) and 110 percent (for double crown).
The relationships of contact angle among different substrates, the role of dehydrating bake on photoresist profile and the relationship between contact angle and photoresist profile are addressed in this paper. Generally speaking, when the HMDS priming time increases, the contact angle of all the substrates increases no matter what the adhesion priming temperature and dehydrating bake time/temperature used. Among these substrates, tungsten silicide always has the largest contact angle and its minimum acceptable priming time is about 5 seconds. Regarding the priming temperature, largest contact angle is obtained with priming temperature around 50 degree(s)C for doped poly, bare silicon, and tungsten silicide substrates, while for Teos substrates there is no significance difference on priming temperature as it's beyond larger than 30 degree(s)C. In terms of dehydration temperature, lower baking temperature results in larger contact angle. However, as far as the photoresist profile is concerned, higher contact angle does not guarantee that profile is vertical without undercut or tailing problems. In view of improving the photoresist profile, the dehydrating bake is unavoidable and the temperature should be around 100 degree(s)C.
Three types of dies on the wafer including dies on wafer edge, dies adjacent to testkey patterns, and dies with asymmetric chip layout have been identified for mistilting on the lithography exposure processes. There are several approaches i.e. dummy die exposed on the wafer edge, various focus offset, and pattern layout modification etc. can alleviate this problem. However, to complete solve these issues rely on the fundamental and methodical improvements on the stepper leveling system and control software.
The lithography processes for the metal layers of stacked DRAM have normally been considered as one of the most important steps to determine the chip yield performance. The severe topography step-height on the metal resist processes normally leads to an insufficient UDOF for production. The Taguchi design of experiment (DOE) method is chosen in this study to optimize the resist processes on metal layers with a 1.0 micrometers topography step. The resist process parameters are arranged into the orthogonal arrays and to experimentally determine the optimized conditions for resist patterned over the severe topography step-height with 1.2 micrometers pitches. The important factors controlling the process window are reported in the paper. An increase of 4 dB in S/N response, which corresponds to an increase of 0.4 micrometers in DOF and 6% in exposure window, is achieved by using the design of the experiment. Furthermore, the control factors to determine the optimized process conditions for thick resist processes on metal topography wafers can be quite different from those for thin resist processes on bare silicone wafers.
The stacked cell design of DRAM processes for lithography considerations has suffered severe topography step-height and unsmooth surface issues. In addition, the stability and uniformity control of thin film processes on the backend process can affect lithography process to a great extent. In this study, the AFM (atomic force microscope) has been used to study topography issues of a typical DRAM process. The detailed information concerning the topography step- height, flow angle, local unsmooth surface, etc., have been clearly identified. These studies provide useful information for future process development and improvement.
I-line lithography, together with single-layer resist processes, practically, have been limited to 0.45 micrometers design rules in the semiconductor industry. For design rules of 0.4 micrometers and below, several contrast enhanced methods have been proposed for i-line lithography, mainly phase shift masks, modified illumination methods, and surface imaging techniques, etc. This paper describes the sub-half micron process performance of 0.48 NA and 0.54 i-line steppers on various topography wafers which are suitable for 0.35 - 0.40 micrometers and 0.40 - 0.45 micrometers design rules. The latest high performance i-line resist and high contrast developing scheme have been chosen for this study. The process windows for the sub-half micron features on various topography wafers are reported. The feasibility to use these processes for the production with lower K1 is also addressed.
The striation problem on 8' topographical wafers is reported. The striation on topographical wafers is not observed on planar wafers. The degree of striation increases with topographical step-height for the traditional photoresist dispense method. In this study, two modified photoresist dispense methods have been adopted for improving striation problems on topographical wafers. The design of experiment by Taguchi method has been used to determine the optimized conditions for the resist dispense methods. The results of signal-to- noise ratios analyses indicate the factors influencing the degree of striation are strongly dependent on the dispense method being used. It is noted that the traditional dispense method only shows a small degree of improvement in striation even by using Taguchi design-of- experiment (DOE). A large degree of improvement in striation can be achieved by using the modified dispense methods suggested in this study. In summary, this study shows the striation problem on 8' topographical wafers can be improved by using the modified dispense methods suggested in the study. The Taguchi design of experiment method is a valuable tool to determine the optimized process conditions.
Proximity effect, in general, is a major concern for submicron lithography. There are two kinds of proximity effect, i.e. global and local proximity effects, normally observed in the submicron lithography processes. Local proximity effect is occurred as a result of interaction between adjacent patterns, in which elbow rounding and proximity effect between adjacent contact holes are two typical examples. Global proximity effect is as a result of thin film interference of photoresist thickness variation over topography. The critical dimension variation between cell array and periphery patterns is a typical case. In this paper we will discuss several process approaches to the solution of global proximity effect. An optimum process to minimize the global proximity effect will be described.