In the MEMS world, increasing attention is being given to 3D devices requiring dual-sided processing. This requires
lithography tools that are able to align a wafer to both its back side as front side. Overlay describes how well front and back side layers are positioned with respect to each other. Currently there is no simple and fast method to qualify the overlay. This paper covers a method of measuring the overlay between front- and back side patterns using a glass substrate. We describe the methods used, special process requirements and measurement data. The main advantages of the presented method are the simplicity of the concept and the need for only basic fab processing equipment. The substrate employed is re-usable and low cost. The results are as follows: 1. Glass wafers can be used to measure front to back side overlay. The accuracy of the proposed method is better than 100 nm (3σ) on ASML PAS 5000/5200 machines. On ASML PAS 5500 steppers, the expected accuracy is better
than 80 nm (3σ). 2. The proposed method of measuring the absolute glass shift, from a glass-on-silicon stack, yields unreliable
information. This is due to deformation of the glass. An alternative method is described which builds on result 1 (above). 3. Processing of glass wafers has been established, and a glass overlay measurement wafer has been defined. 4. The benefit of Anti Reflective (AR) coatings is suspected, but not yet proven. Minimizing bi-refringency does not play a role in the measurement accuracy of glass wafers for overlay measurements.
To validate the Front- To Backwafer Alignment (FTBA) calibration and to investigate process related overlay errors, electrical overlay test structures are used that requires FTBA [1]. Anisotropic KOH etch through the wafer is applied to transfer the backwafer pattern to the frontwafer. Consequently, the crystal orientation introduces an overlay shift. A double exposure method is presented to separate the process-induced shift from the FTBA shift. The process induced overlay shift can run up to 3 μm, large compared to the expected FTBA error (around 0.1 μm). The measured overlay distribution is 0.45 μm (3σ), this includes both waferstepper and process related overlay errors. The overlay distribution, corrected for waferstepper related overlay errors, like lens distortion, resembles the overlay distribution of the bulk micromachining (BMM) process; 0.26 μm (3σ). The procedures described in this work provide a quantitative method of describing the waferstepper and process related front to backwafer overlay errors.
MEMS device fabrication can benefit from accurate front- to backwafer alignment (FTBA) using Wafersteppers. To characterize FTBA an electrical overlay test structure is designed and fabricated to measure front- to backwafer overlay in a bulk micromachining process. Only two lithographic steps are required to fabricate these devices. The conductive film on the frontwafer, TiN, is virtually insensitive for mechanical damage during backwafer processing, and features a low etch rate in anisotropic KOH etching (2.4 nm/hr). Both FTBA overlay and FTBA CD variations are measured. The measurements shows that the front to backwafer overlay accuracy in bulk micro machining are limited by non-lithographic process errors.
A method has been developed by which, after removal of the bulk silicon in a substrate transfer process, the backside of a wafer can be processed with the same lithography as the front side of the wafer. To achieve an accurate front-to-backwafer alignment accuracy, mirror symmetric alignment markers for an ASML PAS5000 waferstepper have been developed and applied in a Silicon-on- Anything process. In this manner minimum dimension low-ohmic contacts were fabricated on the backwafer. The mirror symmetric alignment markers are used in combination with standard overlay test procedures to characterize the front-to backwafer overlay accuracy. The measured overlay errors are divided up in non- mirror symmetric lens distortions and wafer distortion as a result of the substrate transfer process. The practical minimum device feature that can be realized on the backwafer is limited to 0.9-1.2 micrometers as a result of front-to-backwafer overlay errors.
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